Motorola MVME172 manual MC2 Chip

Interrupt Level Register 4 (bits 24-31)	2-94
Interrupt Level Register 4 (bits 16-23)	2-95
Interrupt Level Register 4 (bits 8-15)	2-95
Interrupt Level Register 4 (bits 0-7)	2-96
Vector Base Register	2-96
I/O Control Register 1	2-97
I/O Control Register 2	2-98
I/O Control Register 3	2-98
Miscellaneous Control Register	2-99
GCSR Programming Model	2-101
Programming the GCSR	2-103
VMEchip2 Revision Register	2-105
VMEchip2 ID Register	2-105
VMEchip2 LM/SIG Register	2-105
VMEchip2 Board Status/Control Register	2-107
General Purpose Register 0	2-108
General Purpose Register 1	2-108
General Purpose Register 2	2-109
General Purpose Register 3	2-109
General Purpose Register 4	2-110
General Purpose Register 5	2-110
CHAPTER 3 MC2 Chip
Introduction	3-1
Summary of Major Features	3-1
Functional Description	3-2
MC2 Chip Initialization	3-2
Flash and PROM Interface	3-2
BBRAM Interface	3-3
82596CA LAN Interface	3-3
MPU Port and MPU Channel Attention	3-3
MC68060-Bus Master Support for 82596CA	3-4
LANC Bus Error	3-4
LANC Interrupt	3-5
53C710 SCSI Controller Interface	3-5
SRAM Memory Controller	3-5
NON-ECC DRAM Memory Controller	3-5
Z85230 SCC Interface	3-6
Tick Timers	3-7
Watchdog Timer	3-8

xi