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Motorola MVME172 manual Corresponding INT status bit. In level-sensitive mode

Models: MVME172

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Programming Model

IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control Registers

The registers which control IP_c and IP_d are not used on the 200/300-

Series MVME172.

ADR/SIZ		$FFFBC010 through $FFFBC017 (8 bits each)						4
BIT	7	6	5	4	3	2	1	0
NAME($10)	a0_PLTY	a0_E/L*	a0_INT	a0_IEN	a0_ICLR	a0_IL2	a0_IL1	a0_IL0
NAME($11)	a1_PLTY	a1_E/L*	a1_INT	a1_IEN	a1_ICLR	a1_IL2	a1_IL1	a1_IL0
NAME($12)	b0_PLTY	b0_E/L*	b0_INT	b0_IEN	b0_ICLR	b0_IL2	b0_IL1	b0_IL0
NAME($13)	b1_PLTY	b1_E/L*	b1_INT	b1_IEN	b1_ICLR	b1_IL2	b1_IL1	b1_IL0
NAME($14)	c0_PLTY	c0_E/L*	c0_INT	c0_IEN	c0_ICLR	c0_IL2	c0_IL1	c0_IL0
NAME($15)	c1_PLTY	c1_E/L*	c1_INT	c1_IEN	c1_ICLR	c1_IL2	c1_IL1	c1_IL0
NAME($16)	d0_PLTY	d0_E/L*	d0_INT	d0_IEN	d0_ICLR	d0_IL2	d0_IL1	d0_IL0
NAME($17)	d1_PLTY	d1_E/L* d1_INT		d1_IEN d1_ICLR		d1_IL2	d1_IL1	d1_IL0
OPER	R/W	R/W	R	R/W	C	R/W	R/W	R/W
RESET	0 R	0 R	0 R	0 R	0 R	0 R	0 R	0 R
	IL2-IL0	These three bits select the interrupt level for the
		corresponding IndustryPack interrupt request. Level 0
		does not generate an interrupt.
	ICLR	In edge-sensitive mode, writing a logic 1 to this bit clears
		the corresponding INT status bit. In level-sensitive mode,
		this bit has no function. It always reads as 0.

IEN	When IEN is set, the interrupt is enabled. When IEN is
	cleared, the interrupt is disabled.
INT	When this bit is high, an interrupt is being generated for
	the corresponding IndustryPack IRQ. The interrupt is at
	the level programmed in IL2-IL0.
E/L*	When this bit is high, the interrupt is edge sensitive. When
	the bit is low, the interrupt is level sensitive.

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Motorola MVME172 manual Corresponding INT status bit. In level-sensitive mode, This bit has no function. It always reads as

Contents

VME Embedded Controller Programmer’s Reference Guide MVME172Restricted Rights Legend Preface Recent Updates Page Page Contents VMEchip2 Page Page MC2 Chip Xii IP2 Chip Chapter Mcecc Index Figures Xvii Xviii Overview IntroductionBoard Description and Memory Maps MVME172 Features Summary Feature 200/300-Series Fuses LAN power SCON, LAN, Fuse LAN powerRequirements Functional Description Block DiagramsNo-VMEbus-Interface Option 300-Series MVME172 Block Diagram 500-Series MVME172 Block DiagramVMEchip2 MC2 Chip Address Bit # Redundant Functions in the VMEchip2 and MC2 ChipNormal Address Range Memory MapsVMEbus Interface and VMEchip2 Local Bus Memory Map300-Series MVME172 Local Bus Memory Map Memory Maps 500-Series MVME172 Local Bus Memory Map Cache Accessed Width InhibitDevices Port Software Address Range Memory Maps 300-Series MVME172 Local I/O Devices Memory Map Address Range Devices Accessed Port Size Width$FFFBC000 $FFFBC01F $FFFBC800 $FFFBC81F Memory Maps Address Range Device Port Size Width 500-Series MVME172 Local I/O Devices Memory Map2KB $FFFBC800 $FFFBC81F Board Description and Memory Maps Tables 1-7 through 1-17 give the detailed memory maps for Detailed I/O Memory MapsOffset VMEchip2 Memory Map Sheet 1This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3MC2 Chip Base Address = $FFF42000 MC2 Chip Register MapOffset D31-D24 D23-D16 D15-D8 D7-D0 Address Range Selected Device Port Width Size IP2 Chip Overall Memory MapIP2 Chip Base Address = $FFFBC000 10. IP2 Chip Memory Map Control and Status RegistersDMA Dlbe Chani TBL $51 DMAc INT Dlbe Ipend Chani TBL Ipto Done Mcecc Base Address = $FFF43000 1st $FFF43100 2nd 11. Mcecc Internal Register Memory MapName D31 D30 D29 D28 D27 D26 D25 D24 Z85230 SCC Register Address 12. Z85230 SCC Register Addresses13 CA Ethernet LAN Memory Map 14 C710 Scsi Memory Map 15. MK48T58 BBRAM/TOD Clock Memory Map BBRAM/TOD Clock Memory MapAddress Range Description Size Bytes Local Scsi ID 16. Bbram Configuration Area Memory MapFT = Frequency Test x = Must be set to 17. TOD Clock Memory MapAddress Data Bits Function Ecc1memserial 12 characters are followed by four blanks 3992B03A Interrupt Acknowledge Map VMEbus Memory MapVMEbus Short I/O Memory Map VMEbus Accesses to the Local BusSoftware Support Considerations InterruptsSources of Local Berr Cache CoherencyLocal Bus Time-out VMEbus Berr VMEbus Access Time-outLocal Dram Parity Error Bus Error ProcessingMPU Parity Error Description of Error Conditions on the MVME172MPU TEA Cause Unidentified MPU Off-board ErrorMPU Local Bus Time-out Dmac Parity Error Dmac VMEbus ErrorDmac LTO Error Dmac Off-board ErrorDmac TEA Cause Unidentified LAN Parity ErrorLAN LTO Error LAN Off-Board ErrorScsi Off-Board Error Scsi Parity ErrorScsi LTO Error Example of the Proper Use of Bus Timers MVME172 MC68060 Indivisible Cycles Illegal Access to IP Modules from External VMEbus Masters Page VMEchip2 Summary of Major FeaturesVMEchip2 Introduction Local Bus to VMEbus Interface Functional BlocksVMEchip2 Block Diagram VMEchip2 Local Bus to VMEbus Requester VMEchip2 Functional Blocks VMEbus to Local Bus InterfaceLocal Bus to VMEbus DMA Controller Functional Blocks No Address Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog TimersWatchdog Timer Tick TimersVMEbus Interrupter Iack Daisy-Chain Driver Bus TimerVMEbus System Controller ArbiterLocal Bus Interrupter and Interrupt Handler Reset DriverFunctional Blocks Global Control and Status Registers Lcsr Programming ModelSummary of the Lcsr is shown in Table VMEchip2 Memory Map Lcsr Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map Lcsr Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address RegisterVMEbus Slave Address Translation Address Offset Register Segment Address Translation Size Select Value VMEbus Slave Address Translation Select Register$FFF4000C 16 bits WP2 VMEbus Slave Write Post and Snoop Control RegisterSNP2 BLK VMEbus Slave Address Modifier Select RegisterDAT PGMUSR A32SUP SNP1 WP1ADDER1 Cycles When this bit is high, the first map decoder responds toBlock access cycles A24 access cyclesBit is low, the first map decoder does not respond to A32 access cyclesVMEbus supervisory access cycles. When this bit is low Programming the Local Bus to VMEbus Map DecodersVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits D16 Local Bus Slave VMEbus Master Attribute RegisterDecoder 3. Because the local bus to VMEbus interface Segment defined by map decoder 3. When this bit isNot support block transfers, the block transfer address Segment defined by map decoder 2. When this bit isBus map decoder Decoder 2. Since the local bus to VMEbus interface doesDecoder 1. Because the local bus to VMEbus interface Segment defined by map decoder 1. When this bit isVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN3 Local Bus to VMEbus Enable Control RegisterEN1 EN2Local Bus to VMEbus I/O Control Register I2EN I2WPProgramming the VMEchip2 DMA Controller Dmac Registers Dmac Command Table FormatEntry Function ROM0 Prom Decoder, Sram and DMA Control RegisterSrams TblscLvfair Local Bus to VMEbus Requester Control RegisterLvreql LvrwdRobn DHBDhalt DfairDtbl DENSNP TvmeLinc VincVME AM Dmac VMEbus Address Counter Dmac Local Bus Address CounterDmac VMEbus Address Counter VMEbus Interrupter Control Register Table Address CounterDmac Byte Counter IRQ1S IrqlIrqs IrqcMPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector RegisterTBL Dmac Status RegisterDone VMEVMEbus Arbiter Time-out Control Register Programming the Tick and Watchdog TimersTime on VgtoVato LbtoPrescaler register = 256 B clock MHz Prescaler Control RegisterTick Timer 1 Counter Tick Timer 1 Compare RegisterTick timer 1 Compare Register Tick Timer 2 Counter Tick Timer 2 Compare RegisterTick timer 2 Counter Board Control Register Watchdog Timer Control Register Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control RegisterProgramming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter SummaryDmac Local Bus Interrupter Status Register bits SIG1 LM0LM1 SIG0SW3 SW0SW1 SW2VME4 VME1VME2 VME3Local Bus Interrupter Enable Register bits ESIG1 ELM0ELM1 ESIG0ESW3 ESW0ESW1 ESW2EIRQ4 EIRQ1EIRQ2 EIRQ3Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits Sysf Level WPE Level Interrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ6 VIRQ5 Level VBR Vector Base RegisterControl Register Connects to pin 17 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Enint Miscellaneous Control Register100 Computer Group Literature Center Web Site Gcsr Programming Model 102 Computer Group Literature Center Web Site Gcsr Programming Model Programming the GcsrVMEchip2 Memory Map Gcsr Summary Shows a summary of the GcsrLocal Bus VMEchip2 ID Register VMEchip2 Revision RegisterVMEchip2 LM/SIG Register LM2 RST LM3VMEchip2 Board Status/Control Register ISFGeneral Purpose Register Local Bus $FFF40110/VMEbus $XXY8 16 bits Local Bus $FFF40118/VMEbus $XXYC 16 bits MC2 Chip Flash and Prom Interface MC2 Chip Initialization82596CA LAN Interface Bbram InterfaceMPU Port and MPU Channel Attention MC68060-Bus Master Support for 82596CA Lanc Bus ErrorLanc Interrupt 53C710 Scsi Controller InterfaceSram Memory Controller NON-ECC Dram Memory ControllerDram Performance Z85230 SCC InterfaceClock Budget Operating Conditions Address Range SCC Device Number Tick TimersLocal Bus Timer Watchdog TimerMemory Map of the MC2 Chip Registers Memory Map of the MC2 Chip Registers Programming Model MC2 Chip Revision Register MC2 Chip ID RegisterGeneral Control Register SCCIT10 Number of Z85230s Interrupt Vector Base RegisterInterrupt Source IV3-IV0 Daisy Chain Priority Interrupt Vector Base Register Encoding PriorityTick Timer 1 and 2 Compare and Counter Registers Programming the Tick TimersTick Timer 1 Counter Tick Timer 1 Compare RegisterTick Timer 2 Compare Register LSB Prescaler Count Register Tick Timer 2 CounterTick Timer 1 and 2 Control Registers Prescaler Clock Adjust RegisterTick Timer 1 Control Register Tick Timer 2 Control RegisterOVF3-OVF0 Tick Timer 2 Interrupt Control Register Tick Timer Interrupt Control RegistersTick Timer 4 Interrupt Control Register Tick Timer 3 Interrupt Control RegisterTick Timer 1 Interrupt Control Register IEN Dram Parity Error Interrupt Control RegisterIL2-IL0 IclrSCC Interrupt Control Register Tick Timer 4 Control Register Tick Timer 3 and 4 Control RegistersTick Timer 3 Control Register Dram Space Base Address Register Dram and Sram Memory Controller RegistersDram Space Size Register Sram Space Base Address RegisterDRAM/SRAM Options Register Dram Size Control Bit EncodingDZ2 DZ0 Memory Size 28F020 256K x 8 Flash memory devices are used Sram Size Control Bit EncodingF0 set to a 0 indicates that one 28F016SA 2M x 8 Flash Memory device is used. F0 set to a 1 indicates that fourSZ1 SZ0 Memory Size Sram Space Size RegisterLTO, EXT, Prty Lanc Error Status RegisterPlty 82596CA Lanc Interrupt Control RegisterLanc Bus Error Interrupt Control Register General Purpose Inputs Register Scsi Error Status RegisterV11 MVME172 Version Register Scsi Interrupt Control Register Tick Timer 3 Compare Register Tick Timer 3 and 4 Compare and Counter RegistersTick Timer 3 Counter Tick Timer 4 Counter Tick Timer 4 Compare RegisterBus Clock Register ET2 Prom Access = N Prom Access Time Control RegisterAt 25 MHz where N = At 33 MHz where N = FT2 Flash Access = N Flash Access Time Control RegisterAbort Switch Interrupt Control Register Reset Switch Control Register Watchdog Timer Control Register Wdto These bits define the watchdog time-out period Access and Watchdog Time Base Select RegisterBit Time-out Encoding Dram Control Register Alternate MPU Status RegisterPAREN-PARINT Clock tickProgramming Model Bit Prescaler Count Register IP2 Chip General Description Local Bus to IndustryPack DMA Controllers IP2 Chip Clocking Environments and Performance IP2 Chip Clock Cycles Error Reporting as a Local Bus Master Error ReportingFollowing paragraphs describe the IP2 chip error reporting Error Reporting as a Local Bus SlaveIndustryPack Error Reporting Overall Memory Map This status bit is cleared by writing a one to it This bit is readable and writableRegister Register Name Register Bit Names Offset IP2 Chip Memory Map Control and Status RegistersDMA Rotat Dint Dien Diclr Chani TBL $5B DMAc LB Dmac for Chip Revision Register Chip ID RegisterVector Base Register IV2-0 Interrupt Source IPa, IPb, IPc, IPd Memory Base Address RegistersIPb Memory Base Address Registers IPa or Double Size IPab Memory Base Address RegistersIPd Memory Base Address Registers IPa, IPb, IPc, IPd Memory Size RegistersIPc or Double Size IPcd Memory Base Address Registers Not used on 200/300-Series MVME172BIT NAME$0C When this bit is high, an interrupt is being generated for Corresponding INT status bit. In level-sensitive modeWhen IEN is set, the interrupt is enabled. When IEN is Cleared, the interrupt is disabledMEN IPa, IPb, IPc, and IPd General Control RegistersBTD Memory Space Data Width DERR AERRBERR CERRIP32 Setting IP32 to a one enables the IndustryPack bus toSetting it to a zero will enable 8 MHz operation. In this IP Clock RegisterDMA Arbitration Control Register Where each Dmac has equal access to the MC68060Local bus. If Rotat is set to a one, the priority is fixed RES IP Reset RegisterProgramming the DMA Controllers Control Word Byte Count DMA Control and Status Register Set Definition DMA Enable FunctionIpto DMA Status RegisterDint IpendDIL2-DIL0 DienDEN DMA Control Register Adma Ento ToipDMA Local Bus Address Counter DmaeiDMA Byte Counter DMA IndustryPack Address CounterDMA Table Address Counter IRE Programming the Programmable ClockProgrammable Clock Interrupt Control Register IL2-0PS2-0 Programmable Clock General Control RegisterCLR PLS Programmable Clock Timer RegisterBit Memory Space Local Bus to IndustryPack AddressingComments Local Bus to IndustryPack Addressing $00FFFFFB $7FFFFD IPA6-0 Comments IPa I/O SpaceIPab I/O Space IPA5-0 Comments IPa ID SpaceIP to Local Bus Data Routing Memory Space AccessesThis section shows data routing from an IP to the local bus IP to Local Bus Data Routing Space Lbsize LBA IPA ID Space AccessesMcecc FeaturesPerformance Descriptions Specifications Mcecc SpecificationsCycle Types ECCSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Error ReportingDouble Bit Error Cycle Type = Burst Read or Non-Burst Read Single Bit Error Cycle Type = Scrub Single Bit Error Cycle Type = Non-Burst WriteDouble Bit Error Cycle Type = Non-Burst Write Triple or Greater Bit Error Cycle Type = Non-Burst WriteScrub Error LoggingDouble Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = ScrubRefresh Chip DefaultsArbitration Programming Model Offset Name Mcecc Internal Register Memory Map, PartMcecc Base Address = $FFF43000 1st $FFF43100 2nd RegisterBase BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address D31 D30 D29 D28 D27 D26 D25 D24 Register Bit NamesScrub SAC7 SAC6 SAC5 SAC4 Addr Cntr 1st $FFF43000/2nd $FFF43100 8-bits MSIZ2-MSIZ0 Memory Configuration RegisterRB3 Read Bit 3 is a read only bit that is always Dummy RegisterRB4 Read Bit 4 is a read only bit that is always Difference from MEMC040 none Base Address RegisterBit assignments for the Base Address Register are RWB3 Read/Write Bit 3 is a general purpose read/write bit Bit assignments for the Dram Control Register areRWB5 Read/Write Bit 5 is a general purpose read/write bit Bclk Frequency Register Data Control Register Mcecc Scrub Control Register This register contains bits 7-0 of the Scrub Period Register Scrub Period Register BitsScrub Time On/Time Off Register Chip Prescaler CounterSTOFF2-STOFF0 Scrubber Time Off STON2-STON0Scrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF4304C/2nd $FFF4314C 8-bits Error Logger Register Error Address Bits 1st $FFF43064/2nd $FFF43164 8-bits Defaults Register Error Syndrome RegisterRSIZ2-RSIZ0 Dram Array Size SELI1, SELI0Register Base Address Nocache RESST2-RESST0Initialization Mcecc Syndrome Decode Bank in Error Bit in Error Syndrome CodeBank C Bank a Mcecc Document Title Motorola Publication Number Motorola Computer Group DocumentsManufacturers’ Documents Literature UpdatesTable A-2. Manufacturers’ Documents Table A-2. Manufacturers’ Documents Related Documentation VMEchip2 Tick Timer 1 Periodic Interrupt Example BUsing Interrupts on the MVME172Refer to the Vector Base Register Step Register and Address Action and ReferenceUsing Interrupts on the MVME172 Page Index IN-2 DMA Gcsr Lanc IN-6 MPU SCC Scsi Mcecc IN-10 IN-11 Index MVME172 MVME172 Programmer’s Reference Guide