LCSR Programming Model

Local Bus Interrupter Status Register (bits 16-23)

ADR/SIZ

 

 

$FFF40068 (8 bits of 32)

 

 

 

 

 

 

 

 

 

 

 

BIT

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

NAME

VIA

DMA

SIG3

SIG2

SIG1

SIG0

LM1

LM0

 

 

 

 

 

 

 

 

 

OPER

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

RESET

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

 

 

 

 

 

 

 

 

 

This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated. The interrupt status bits are:

LM0

GCSR LM0 interrupt.

LM1

GCSR LM1 interrupt.

SIG0

GCSR SIG0 interrupt.

SIG1

GCSR SIG1 interrupt.

SIG2

GCSR SIG2 interrupt.

SIG3

GCSR SIG3 interrupt.

DMA

DMAC interrupt.

VIA

VMEbus interrupter acknowledge interrupt.

2

http://www.mcg.mot.com/literature

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Image 157
Motorola MVME172 manual LM0, LM1, SIG0, SIG1, SIG2, SIG3, Dma, Via