Refresh, Arbitration, Chip Defaults | Motorola MVME172 specs

5

MCECC

occurs, the local bus master is notified if such interrupts are enabled in the control register. A software bit is available to disable the read portion of the scrub cycle.

Refresh

The MCECC pair provides refresh control for the DRAM. It performs a single CAS-before-RAS refresh cycle to the two DRAM blocks approximately once every 15.6 μs. To prevent undue noise generation, the MCECC pair does not refresh both blocks at once, but staggers the refreshes by one clock cycle.

Arbitration

The MCECC pair has 3 different entities that can request use of the DRAM cycle controller: (1) the local bus master, (2) the refresher, and (3) the scrubber.

The MCECC pair arbiter accepts requests and provides grants to the requesting entities as follows:

Priority is (highest to lowest) refresher, local bus, and scrubber.

When no requests are pending, the arbiter defaults to providing a local bus grant for fast response to local bus cycles.

Although the arbiter operates on a priority basis, it also performs a pseudo round robin algorithm in order to prevent starving any of the requesting entities.

Chip Defaults

Some jumper option kinds of parameters need to be configured in the MCECC pair. These options include DRAM size, DRAM speed, Control and Status Register Selection, etc. Rather than use pins (which are extremely scarce) for each of the options, the MCECC pair is designed to have an external PAL or other equivalent logic provide this information at reset time, using one pin as a serial input. The information provided to this input pin at power-up-reset or local bus reset, is called the "reset serial bit

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Motorola MVME172 manual Refresh, Arbitration, Chip Defaults

Contents

MVME172 VME Embedded Controller Programmer’s Reference Guide Restricted Rights Legend Preface Recent Updates Page Page Contents VMEchip2 Page Page MC2 Chip Xii IP2 Chip Chapter Mcecc Index Figures Xvii Xviii Introduction Overview Board Description and Memory Maps MVME172 Features Summary Feature 200/300-Series Fuses LAN power SCON, LAN, Fuse LAN powerRequirements Functional Description Block DiagramsNo-VMEbus-Interface Option 300-Series MVME172 Block Diagram Block Diagram 500-Series MVME172 Redundant Functions in the VMEchip2 and MC2 Chip VMEchip2 MC2 Chip Address Bit # Local Bus Memory Map Memory MapsVMEbus Interface and VMEchip2 Normal Address Range 300-Series MVME172 Local Bus Memory Map Memory Maps 500-Series MVME172 Local Bus Memory Map Cache Accessed Width InhibitDevices Port Software Address Range Memory Maps Address Range Devices Accessed Port Size Width 300-Series MVME172 Local I/O Devices Memory Map $FFFBC000 $FFFBC01F $FFFBC800 $FFFBC81F Memory Maps 500-Series MVME172 Local I/O Devices Memory Map Address Range Device Port Size Width 2KB $FFFBC800 $FFFBC81F Board Description and Memory Maps Detailed I/O Memory Maps Tables 1-7 through 1-17 give the detailed memory maps for VMEchip2 Memory Map Sheet 1 Offset This sheet begins on facing VMEchip2 Memory Map Sheet 2 PRE Compare Register Counter Overflow VMEchip2 Memory Map Sheet 3 Offsets Bit Numbers MC2 Chip Base Address = $FFF42000 MC2 Chip Register MapOffset D31-D24 D23-D16 D15-D8 D7-D0 IP2 Chip Overall Memory Map Address Range Selected Device Port Width Size 10. IP2 Chip Memory Map Control and Status Registers IP2 Chip Base Address = $FFFBC000 DMA Dlbe Chani TBL $51 DMAc INT Dlbe Ipend Chani TBL Ipto Done 11. Mcecc Internal Register Memory Map Mcecc Base Address = $FFF43000 1st $FFF43100 2nd Name D31 D30 D29 D28 D27 D26 D25 D24 12. Z85230 SCC Register Addresses Z85230 SCC Register Address 13 CA Ethernet LAN Memory Map 14 C710 Scsi Memory Map 15. MK48T58 BBRAM/TOD Clock Memory Map BBRAM/TOD Clock Memory MapAddress Range Description Size Bytes 16. Bbram Configuration Area Memory Map Local Scsi ID FT = Frequency Test x = Must be set to 17. TOD Clock Memory MapAddress Data Bits Function Ecc1memserial 12 characters are followed by four blanks 3992B03A VMEbus Memory Map Interrupt Acknowledge Map Interrupts VMEbus Accesses to the Local BusSoftware Support Considerations VMEbus Short I/O Memory Map Sources of Local Berr Cache CoherencyLocal Bus Time-out Bus Error Processing VMEbus Access Time-outLocal Dram Parity Error VMEbus Berr Description of Error Conditions on the MVME172 MPU Parity Error MPU TEA Cause Unidentified MPU Off-board ErrorMPU Local Bus Time-out Dmac VMEbus Error Dmac Parity Error Dmac Off-board Error Dmac LTO Error LAN Parity Error Dmac TEA Cause Unidentified LAN Off-Board Error LAN LTO Error Scsi Off-Board Error Scsi Parity ErrorScsi LTO Error Example of the Proper Use of Bus Timers MVME172 MC68060 Indivisible Cycles Illegal Access to IP Modules from External VMEbus Masters Page Summary of Major Features VMEchip2 VMEchip2 Introduction Functional Blocks Local Bus to VMEbus Interface VMEchip2 Block Diagram VMEchip2 Local Bus to VMEbus Requester VMEchip2 VMEbus to Local Bus Interface Functional Blocks Local Bus to VMEbus DMA Controller Functional Blocks No Address Increment DMA Transfers Dmac VMEbus Requester Tick and Watchdog Timers Prescaler Tick Timers Watchdog Timer VMEbus Interrupter Arbiter Bus TimerVMEbus System Controller Iack Daisy-Chain Driver Reset Driver Local Bus Interrupter and Interrupt Handler Functional Blocks Lcsr Programming Model Global Control and Status Registers Summary of the Lcsr is shown in Table VMEchip2 Memory Map Lcsr Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map Lcsr Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Ending Address Register VMEbus Slave Starting Address Register VMEbus Slave Address Translation Address Offset Register VMEbus Slave Address Translation Select Register Segment Address Translation Size Select Value $FFF4000C 16 bits WP2 VMEbus Slave Write Post and Snoop Control RegisterSNP2 PGM VMEbus Slave Address Modifier Select RegisterDAT BLK USR A32SUP SNP1 WP1ADDER1 A24 access cycles When this bit is high, the first map decoder responds toBlock access cycles Cycles Programming the Local Bus to VMEbus Map Decoders A32 access cyclesVMEbus supervisory access cycles. When this bit is low Bit is low, the first map decoder does not respond to VMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register D16 Segment defined by map decoder 3. When this bit is Decoder 3. Because the local bus to VMEbus interface Decoder 2. Since the local bus to VMEbus interface does Segment defined by map decoder 2. When this bit isBus map decoder Not support block transfers, the block transfer address Segment defined by map decoder 1. When this bit is Decoder 1. Because the local bus to VMEbus interface VMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN2 Local Bus to VMEbus Enable Control RegisterEN1 EN3 Local Bus to VMEbus I/O Control Register I2WP I2EN Programming the VMEchip2 DMA Controller Dmac Registers Dmac Command Table FormatEntry Function Tblsc Prom Decoder, Sram and DMA Control RegisterSrams ROM0 Lvrwd Local Bus to VMEbus Requester Control RegisterLvreql Lvfair DHB Robn DEN DfairDtbl Dhalt Vinc TvmeLinc SNP VME AM Dmac VMEbus Address Counter Dmac Local Bus Address CounterDmac VMEbus Address Counter VMEbus Interrupter Control Register Table Address CounterDmac Byte Counter Irqc IrqlIrqs IRQ1S VMEbus Interrupter Vector Register MPU Status and DMA Interrupt Count Register VME Dmac Status RegisterDone TBL Programming the Tick and Watchdog Timers VMEbus Arbiter Time-out Control Register Vgto Time on Lbto Vato Prescaler Control Register Prescaler register = 256 B clock MHz Tick Timer 1 Counter Tick Timer 1 Compare RegisterTick timer 1 Compare Register Tick Timer 2 Counter Tick Timer 2 Compare RegisterTick timer 2 Counter Board Control Register Watchdog Timer Control Register Tick Timer 2 Control Register Tick Timer 1 Control Register Prescaler Counter Programming the Local Bus Interrupter Local Bus Interrupter Summary Interrupt Vector Priority for Simultaneous Interrupts Dmac Local Bus Interrupter Status Register bits SIG0 LM0LM1 SIG1 SW2 SW0SW1 SW3 VME3 VME1VME2 VME4 Local Bus Interrupter Enable Register bits ESIG0 ELM0ELM1 ESIG1 ESW2 ESW0ESW1 ESW3 EIRQ3 EIRQ1EIRQ2 EIRQ4 Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits Sysf Level WPE Level Interrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ6 VIRQ5 Level Vector Base Register VBR Control Register Connects to pin 17 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Miscellaneous Control Register Enint 100 Computer Group Literature Center Web Site Gcsr Programming Model 102 Computer Group Literature Center Web Site Programming the Gcsr Gcsr Programming Model VMEchip2 Memory Map Gcsr Summary Shows a summary of the GcsrLocal Bus VMEchip2 ID Register VMEchip2 Revision RegisterVMEchip2 LM/SIG Register LM2 ISF LM3VMEchip2 Board Status/Control Register RST General Purpose Register Local Bus $FFF40110/VMEbus $XXY8 16 bits Local Bus $FFF40118/VMEbus $XXYC 16 bits MC2 Chip MC2 Chip Initialization Flash and Prom Interface 82596CA LAN Interface Bbram InterfaceMPU Port and MPU Channel Attention Lanc Bus Error MC68060-Bus Master Support for 82596CA NON-ECC Dram Memory Controller 53C710 Scsi Controller InterfaceSram Memory Controller Lanc Interrupt Dram Performance Z85230 SCC InterfaceClock Budget Operating Conditions Tick Timers Address Range SCC Device Number Local Bus Timer Watchdog TimerMemory Map of the MC2 Chip Registers Memory Map of the MC2 Chip Registers Programming Model MC2 Chip ID Register MC2 Chip Revision Register General Control Register Interrupt Vector Base Register SCCIT10 Number of Z85230s Interrupt Vector Base Register Encoding Priority Interrupt Source IV3-IV0 Daisy Chain Priority Programming the Tick Timers Tick Timer 1 and 2 Compare and Counter Registers Tick Timer 1 Counter Tick Timer 1 Compare RegisterTick Timer 2 Compare Register Tick Timer 2 Counter LSB Prescaler Count Register Prescaler Clock Adjust Register Tick Timer 1 and 2 Control Registers Tick Timer 1 Control Register Tick Timer 2 Control RegisterOVF3-OVF0 Tick Timer 3 Interrupt Control Register Tick Timer Interrupt Control RegistersTick Timer 4 Interrupt Control Register Tick Timer 2 Interrupt Control Register Tick Timer 1 Interrupt Control Register Iclr Dram Parity Error Interrupt Control RegisterIL2-IL0 IEN SCC Interrupt Control Register Tick Timer 4 Control Register Tick Timer 3 and 4 Control RegistersTick Timer 3 Control Register Dram and Sram Memory Controller Registers Dram Space Base Address Register Sram Space Base Address Register Dram Space Size Register DRAM/SRAM Options Register Dram Size Control Bit EncodingDZ2 DZ0 Memory Size Memory device is used. F0 set to a 1 indicates that four Sram Size Control Bit EncodingF0 set to a 0 indicates that one 28F016SA 2M x 8 Flash 28F020 256K x 8 Flash memory devices are used Sram Space Size Register SZ1 SZ0 Memory Size Lanc Error Status Register LTO, EXT, Prty 82596CA Lanc Interrupt Control Register Plty Lanc Bus Error Interrupt Control Register Scsi Error Status Register General Purpose Inputs Register V11 MVME172 Version Register Scsi Interrupt Control Register Tick Timer 3 Compare Register Tick Timer 3 and 4 Compare and Counter RegistersTick Timer 3 Counter Tick Timer 4 Counter Tick Timer 4 Compare RegisterBus Clock Register ET2 Prom Access = N Prom Access Time Control RegisterAt 25 MHz where N = At 33 MHz where N = Flash Access Time Control Register FT2 Flash Access = N Abort Switch Interrupt Control Register Reset Switch Control Register Watchdog Timer Control Register Wdto These bits define the watchdog time-out period Access and Watchdog Time Base Select RegisterBit Time-out Encoding Dram Control Register Clock tick MPU Status RegisterPAREN-PARINT Alternate Programming Model Bit Prescaler Count Register IP2 Chip General Description Local Bus to IndustryPack DMA Controllers IP2 Chip Clocking Environments and Performance IP2 Chip Clock Cycles Error Reporting as a Local Bus Slave Error ReportingFollowing paragraphs describe the IP2 chip error reporting Error Reporting as a Local Bus Master IndustryPack Error Reporting Overall Memory Map This bit is readable and writable This status bit is cleared by writing a one to it IP2 Chip Memory Map Control and Status Registers Register Register Name Register Bit Names Offset DMA Rotat Dint Dien Diclr Chani TBL $5B DMAc LB Dmac for Chip ID Register Chip Revision Register Vector Base Register IPa, IPb, IPc, IPd Memory Base Address Registers IV2-0 Interrupt Source IPa or Double Size IPab Memory Base Address Registers IPb Memory Base Address Registers Not used on 200/300-Series MVME172 IPa, IPb, IPc, IPd Memory Size RegistersIPc or Double Size IPcd Memory Base Address Registers IPd Memory Base Address Registers BIT NAME$0C Cleared, the interrupt is disabled Corresponding INT status bit. In level-sensitive modeWhen IEN is set, the interrupt is enabled. When IEN is When this bit is high, an interrupt is being generated for IPa, IPb, IPc, and IPd General Control Registers MEN BTD Memory Space Data Width CERR AERRBERR DERR IP Clock Register Setting IP32 to a one enables the IndustryPack bus toSetting it to a zero will enable 8 MHz operation. In this IP32 DMA Arbitration Control Register Where each Dmac has equal access to the MC68060Local bus. If Rotat is set to a one, the priority is fixed IP Reset Register RES Programming the DMA Controllers Control Word Byte Count DMA Enable Function DMA Control and Status Register Set Definition DMA Status Register Ipto Dien IpendDIL2-DIL0 Dint DEN DMA Control Register Adma Toip Ento Dmaei DMA Local Bus Address Counter DMA IndustryPack Address Counter DMA Byte Counter DMA Table Address Counter IL2-0 Programming the Programmable ClockProgrammable Clock Interrupt Control Register IRE PS2-0 Programmable Clock General Control RegisterCLR Programmable Clock Timer Register PLS Bit Memory Space Local Bus to IndustryPack AddressingComments Local Bus to IndustryPack Addressing $00FFFFFB $7FFFFD IPa I/O Space IPA6-0 Comments IPab I/O Space IPa ID Space IPA5-0 Comments IP to Local Bus Data Routing Memory Space AccessesThis section shows data routing from an IP to the local bus IP to Local Bus Data Routing ID Space Accesses Space Lbsize LBA IPA Features Mcecc Performance Mcecc Specifications Descriptions Specifications ECC Cycle Types Single Bit Error Cycle Type = Burst Read or Non-Burst Read Error ReportingDouble Bit Error Cycle Type = Burst Read or Non-Burst Read Triple or Greater Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = Non-Burst WriteDouble Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Scrub Error LoggingDouble Bit Error Cycle Type = Scrub Scrub Refresh Chip DefaultsArbitration Programming Model Register Mcecc Internal Register Memory Map, PartMcecc Base Address = $FFF43000 1st $FFF43100 2nd Offset Name Base BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address Register Bit Names D31 D30 D29 D28 D27 D26 D25 D24 Scrub SAC7 SAC6 SAC5 SAC4 Addr Cntr 1st $FFF43000/2nd $FFF43100 8-bits Memory Configuration Register MSIZ2-MSIZ0 RB3 Read Bit 3 is a read only bit that is always Dummy RegisterRB4 Read Bit 4 is a read only bit that is always Difference from MEMC040 none Base Address RegisterBit assignments for the Base Address Register are Bit assignments for the Dram Control Register are RWB3 Read/Write Bit 3 is a general purpose read/write bit RWB5 Read/Write Bit 5 is a general purpose read/write bit Bclk Frequency Register Data Control Register Mcecc Scrub Control Register Scrub Period Register Bits This register contains bits 7-0 of the Scrub Period Register Scrub Time On/Time Off Register Chip Prescaler CounterSTOFF2-STOFF0 Scrubber Time Off STON2-STON0Scrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF4304C/2nd $FFF4314C 8-bits Error Logger Register Error Address Bits 1st $FFF43064/2nd $FFF43164 8-bits Defaults Register Error Syndrome RegisterRSIZ2-RSIZ0 Dram Array Size SELI1, SELI0Register Base Address RESST2-RESST0 Nocache Initialization Mcecc Bank in Error Bit in Error Syndrome Code Syndrome Decode Bank C Bank a Mcecc Motorola Computer Group Documents Document Title Motorola Publication Number Manufacturers’ Documents Literature UpdatesTable A-2. Manufacturers’ Documents Table A-2. Manufacturers’ Documents Related Documentation BUsing Interrupts on the MVME172 VMEchip2 Tick Timer 1 Periodic Interrupt Example Step Register and Address Action and Reference Refer to the Vector Base Register Using Interrupts on the MVME172 Page Index IN-2 DMA Gcsr Lanc IN-6 MPU SCC Scsi Mcecc IN-10 IN-11 Index MVME172 Programmer’s Reference Guide MVME172