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Motorola MVME172 manual DMA Enable Function, DMA Control and Status Register Set Definition

Models: MVME172

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Programming Model

DMA Enable Function

There are certain DMA channel contexts which are illegal. If an attempt is made to program the DMA control register 1 for each channel a and b or c and d to an illegal state, the DEN (DMA enable control bit) will not set when it is loaded to a one via a processor store instruction. This condition can be tested by writing the DEN bit to a one and reading a zero. Refer to the description of the DMA Enable Register for the required programming sequence of the control registers and enable bits.

The following are legal contexts for DMA channel configurations. Note that configuration rules for DMA controllers for IP_a and IP_b are defined. The same relationships exist for IP_c and IP_d.

❏If IP_a data bus is 8 or 16 bits, there are not any restrictions placed on IP_b.

❏If IP_a data bus is 32 bits and the ADMA mode is selected, then the DMA controller associated with IP_b cannot be used.

❏If A_CH1 bit is set in the DMA controller register associated with IP_b and both channel A and B operate in the SDMA mode, then the DMA channels associated with IP_a and IP_b can both be used if the data width for channel A and B are set equal. This case allows the DMA channel that normally re- sponds to IP_b-DMAreq_0 pin to respond to IP_a-DMAreq_1 pin. This enables full duplex communications operation at IP_a.

DMA Control and Status Register Set Definition

The four sets of DMA controller CSRs are almost identical in functionality. Each register set is grouped as DMACa, DMACb, DMACc, and DMACd. These register sets are shown pictorially in the CSR register summary section. Only one register set is defined except that the offset is noted for the four possible values. Refer to the definitions of bit 1 of the DMA Control Register 1 for a description of how the register sets are associated with the physical DMA request from the Industry Packs.

The registers which control IP_c and IP_d are not used on the 200/300- Series MVME172.

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Motorola MVME172 manual DMA Enable Function, DMA Control and Status Register Set Definition

Contents

VME Embedded Controller Programmer’s Reference Guide MVME172Restricted Rights Legend Preface Recent Updates Page Page Contents VMEchip2 Page Page MC2 Chip Xii IP2 Chip Chapter Mcecc Index Figures Xvii Xviii Overview IntroductionBoard Description and Memory Maps MVME172 Features Summary Requirements Fuses LAN power SCON, LAN, Fuse LAN powerFeature 200/300-Series No-VMEbus-Interface Option Block DiagramsFunctional Description 300-Series MVME172 Block Diagram 500-Series MVME172 Block DiagramVMEchip2 MC2 Chip Address Bit # Redundant Functions in the VMEchip2 and MC2 ChipVMEbus Interface and VMEchip2 Memory MapsLocal Bus Memory Map Normal Address Range300-Series MVME172 Local Bus Memory Map Memory Maps Devices Port Software Address Range Cache Accessed Width Inhibit500-Series MVME172 Local Bus Memory Map Memory Maps 300-Series MVME172 Local I/O Devices Memory Map Address Range Devices Accessed Port Size Width$FFFBC000 $FFFBC01F $FFFBC800 $FFFBC81F Memory Maps Address Range Device Port Size Width 500-Series MVME172 Local I/O Devices Memory Map2KB $FFFBC800 $FFFBC81F Board Description and Memory Maps Tables 1-7 through 1-17 give the detailed memory maps for Detailed I/O Memory MapsOffset VMEchip2 Memory Map Sheet 1This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3Offset D31-D24 D23-D16 D15-D8 D7-D0 MC2 Chip Register MapMC2 Chip Base Address = $FFF42000 Address Range Selected Device Port Width Size IP2 Chip Overall Memory MapIP2 Chip Base Address = $FFFBC000 10. IP2 Chip Memory Map Control and Status RegistersDMA Dlbe Chani TBL $51 DMAc INT Dlbe Ipend Chani TBL Ipto Done Mcecc Base Address = $FFF43000 1st $FFF43100 2nd 11. Mcecc Internal Register Memory MapName D31 D30 D29 D28 D27 D26 D25 D24 Z85230 SCC Register Address 12. Z85230 SCC Register Addresses13 CA Ethernet LAN Memory Map 14 C710 Scsi Memory Map Address Range Description Size Bytes BBRAM/TOD Clock Memory Map15. MK48T58 BBRAM/TOD Clock Memory Map Local Scsi ID 16. Bbram Configuration Area Memory MapAddress Data Bits Function 17. TOD Clock Memory MapFT = Frequency Test x = Must be set to Ecc1memserial 12 characters are followed by four blanks 3992B03A Interrupt Acknowledge Map VMEbus Memory MapSoftware Support Considerations VMEbus Accesses to the Local BusInterrupts VMEbus Short I/O Memory MapLocal Bus Time-out Cache CoherencySources of Local Berr Local Dram Parity Error VMEbus Access Time-outBus Error Processing VMEbus BerrMPU Parity Error Description of Error Conditions on the MVME172MPU Local Bus Time-out MPU Off-board ErrorMPU TEA Cause Unidentified Dmac Parity Error Dmac VMEbus ErrorDmac LTO Error Dmac Off-board ErrorDmac TEA Cause Unidentified LAN Parity ErrorLAN LTO Error LAN Off-Board ErrorScsi LTO Error Scsi Parity ErrorScsi Off-Board Error Example of the Proper Use of Bus Timers MVME172 MC68060 Indivisible Cycles Illegal Access to IP Modules from External VMEbus Masters Page VMEchip2 Summary of Major FeaturesVMEchip2 Introduction Local Bus to VMEbus Interface Functional BlocksVMEchip2 Block Diagram VMEchip2 Local Bus to VMEbus Requester VMEchip2 Functional Blocks VMEbus to Local Bus InterfaceLocal Bus to VMEbus DMA Controller Functional Blocks No Address Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog TimersWatchdog Timer Tick TimersVMEbus Interrupter VMEbus System Controller Bus TimerArbiter Iack Daisy-Chain DriverLocal Bus Interrupter and Interrupt Handler Reset DriverFunctional Blocks Global Control and Status Registers Lcsr Programming ModelSummary of the Lcsr is shown in Table VMEchip2 Memory Map Lcsr Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map Lcsr Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address RegisterVMEbus Slave Address Translation Address Offset Register Segment Address Translation Size Select Value VMEbus Slave Address Translation Select Register$FFF4000C 16 bits SNP2 VMEbus Slave Write Post and Snoop Control RegisterWP2 DAT VMEbus Slave Address Modifier Select RegisterPGM BLKSUP A32USR ADDER1 WP1SNP1 Block access cycles When this bit is high, the first map decoder responds toA24 access cycles CyclesVMEbus supervisory access cycles. When this bit is low A32 access cyclesProgramming the Local Bus to VMEbus Map Decoders Bit is low, the first map decoder does not respond toVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits D16 Local Bus Slave VMEbus Master Attribute RegisterDecoder 3. Because the local bus to VMEbus interface Segment defined by map decoder 3. When this bit isBus map decoder Segment defined by map decoder 2. When this bit isDecoder 2. Since the local bus to VMEbus interface does Not support block transfers, the block transfer addressDecoder 1. Because the local bus to VMEbus interface Segment defined by map decoder 1. When this bit isVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN1 Local Bus to VMEbus Enable Control RegisterEN2 EN3Local Bus to VMEbus I/O Control Register I2EN I2WPProgramming the VMEchip2 DMA Controller Entry Function Dmac Command Table FormatDmac Registers Srams Prom Decoder, Sram and DMA Control RegisterTblsc ROM0Lvreql Local Bus to VMEbus Requester Control RegisterLvrwd LvfairRobn DHBDtbl DfairDEN DhaltLinc TvmeVinc SNPVME AM Dmac VMEbus Address Counter Dmac Local Bus Address CounterDmac VMEbus Address Counter Dmac Byte Counter Table Address CounterVMEbus Interrupter Control Register Irqs IrqlIrqc IRQ1SMPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector RegisterDone Dmac Status RegisterVME TBLVMEbus Arbiter Time-out Control Register Programming the Tick and Watchdog TimersTime on VgtoVato LbtoPrescaler register = 256 B clock MHz Prescaler Control RegisterTick timer 1 Compare Register Tick Timer 1 Compare RegisterTick Timer 1 Counter Tick timer 2 Counter Tick Timer 2 Compare RegisterTick Timer 2 Counter Board Control Register Watchdog Timer Control Register Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control RegisterProgramming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter SummaryDmac Local Bus Interrupter Status Register bits LM1 LM0SIG0 SIG1SW1 SW0SW2 SW3VME2 VME1VME3 VME4Local Bus Interrupter Enable Register bits ELM1 ELM0ESIG0 ESIG1ESW1 ESW0ESW2 ESW3EIRQ2 EIRQ1EIRQ3 EIRQ4Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits Sysf Level WPE Level Interrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ6 VIRQ5 Level VBR Vector Base RegisterControl Register Connects to pin 18 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 17 of the Remote Status and Control Enint Miscellaneous Control Register100 Computer Group Literature Center Web Site Gcsr Programming Model 102 Computer Group Literature Center Web Site Gcsr Programming Model Programming the GcsrLocal Bus Shows a summary of the GcsrVMEchip2 Memory Map Gcsr Summary VMEchip2 LM/SIG Register VMEchip2 Revision RegisterVMEchip2 ID Register LM2 VMEchip2 Board Status/Control Register LM3ISF RSTGeneral Purpose Register Local Bus $FFF40110/VMEbus $XXY8 16 bits Local Bus $FFF40118/VMEbus $XXYC 16 bits MC2 Chip Flash and Prom Interface MC2 Chip InitializationMPU Port and MPU Channel Attention Bbram Interface82596CA LAN Interface MC68060-Bus Master Support for 82596CA Lanc Bus ErrorSram Memory Controller 53C710 Scsi Controller InterfaceNON-ECC Dram Memory Controller Lanc InterruptClock Budget Operating Conditions Z85230 SCC InterfaceDram Performance Address Range SCC Device Number Tick TimersMemory Map of the MC2 Chip Registers Watchdog TimerLocal Bus Timer Memory Map of the MC2 Chip Registers Programming Model MC2 Chip Revision Register MC2 Chip ID RegisterGeneral Control Register SCCIT10 Number of Z85230s Interrupt Vector Base RegisterInterrupt Source IV3-IV0 Daisy Chain Priority Interrupt Vector Base Register Encoding PriorityTick Timer 1 and 2 Compare and Counter Registers Programming the Tick TimersTick Timer 2 Compare Register Tick Timer 1 Compare RegisterTick Timer 1 Counter LSB Prescaler Count Register Tick Timer 2 CounterTick Timer 1 and 2 Control Registers Prescaler Clock Adjust RegisterOVF3-OVF0 Tick Timer 2 Control RegisterTick Timer 1 Control Register Tick Timer 4 Interrupt Control Register Tick Timer Interrupt Control RegistersTick Timer 3 Interrupt Control Register Tick Timer 2 Interrupt Control RegisterTick Timer 1 Interrupt Control Register IL2-IL0 Dram Parity Error Interrupt Control RegisterIclr IENSCC Interrupt Control Register Tick Timer 3 Control Register Tick Timer 3 and 4 Control RegistersTick Timer 4 Control Register Dram Space Base Address Register Dram and Sram Memory Controller RegistersDram Space Size Register Sram Space Base Address RegisterDZ2 DZ0 Memory Size Dram Size Control Bit EncodingDRAM/SRAM Options Register F0 set to a 0 indicates that one 28F016SA 2M x 8 Flash Sram Size Control Bit EncodingMemory device is used. F0 set to a 1 indicates that four 28F020 256K x 8 Flash memory devices are usedSZ1 SZ0 Memory Size Sram Space Size RegisterLTO, EXT, Prty Lanc Error Status RegisterPlty 82596CA Lanc Interrupt Control RegisterLanc Bus Error Interrupt Control Register General Purpose Inputs Register Scsi Error Status RegisterV11 MVME172 Version Register Scsi Interrupt Control Register Tick Timer 3 Counter Tick Timer 3 and 4 Compare and Counter RegistersTick Timer 3 Compare Register Bus Clock Register Tick Timer 4 Compare RegisterTick Timer 4 Counter At 25 MHz where N = At 33 MHz where N = Prom Access Time Control RegisterET2 Prom Access = N FT2 Flash Access = N Flash Access Time Control RegisterAbort Switch Interrupt Control Register Reset Switch Control Register Watchdog Timer Control Register Bit Time-out Encoding Access and Watchdog Time Base Select RegisterWdto These bits define the watchdog time-out period Dram Control Register PAREN-PARINT MPU Status RegisterClock tick AlternateProgramming Model Bit Prescaler Count Register IP2 Chip General Description Local Bus to IndustryPack DMA Controllers IP2 Chip Clocking Environments and Performance IP2 Chip Clock Cycles Following paragraphs describe the IP2 chip error reporting Error ReportingError Reporting as a Local Bus Slave Error Reporting as a Local Bus MasterIndustryPack Error Reporting Overall Memory Map This status bit is cleared by writing a one to it This bit is readable and writableRegister Register Name Register Bit Names Offset IP2 Chip Memory Map Control and Status RegistersDMA Rotat Dint Dien Diclr Chani TBL $5B DMAc LB Dmac for Chip Revision Register Chip ID RegisterVector Base Register IV2-0 Interrupt Source IPa, IPb, IPc, IPd Memory Base Address RegistersIPb Memory Base Address Registers IPa or Double Size IPab Memory Base Address RegistersIPc or Double Size IPcd Memory Base Address Registers IPa, IPb, IPc, IPd Memory Size RegistersNot used on 200/300-Series MVME172 IPd Memory Base Address RegistersBIT NAME$0C When IEN is set, the interrupt is enabled. When IEN is Corresponding INT status bit. In level-sensitive modeCleared, the interrupt is disabled When this bit is high, an interrupt is being generated forMEN IPa, IPb, IPc, and IPd General Control RegistersBTD Memory Space Data Width BERR AERRCERR DERRSetting it to a zero will enable 8 MHz operation. In this Setting IP32 to a one enables the IndustryPack bus toIP Clock Register IP32Local bus. If Rotat is set to a one, the priority is fixed Where each Dmac has equal access to the MC68060DMA Arbitration Control Register RES IP Reset RegisterProgramming the DMA Controllers Control Word Byte Count DMA Control and Status Register Set Definition DMA Enable FunctionIpto DMA Status RegisterDIL2-DIL0 IpendDien DintDEN DMA Control Register Adma Ento ToipDMA Local Bus Address Counter DmaeiDMA Byte Counter DMA IndustryPack Address CounterDMA Table Address Counter Programmable Clock Interrupt Control Register Programming the Programmable ClockIL2-0 IRECLR Programmable Clock General Control RegisterPS2-0 PLS Programmable Clock Timer RegisterComments Local Bus to IndustryPack AddressingBit Memory Space Local Bus to IndustryPack Addressing $00FFFFFB $7FFFFD IPA6-0 Comments IPa I/O SpaceIPab I/O Space IPA5-0 Comments IPa ID SpaceThis section shows data routing from an IP to the local bus Memory Space AccessesIP to Local Bus Data Routing IP to Local Bus Data Routing Space Lbsize LBA IPA ID Space AccessesMcecc FeaturesPerformance Descriptions Specifications Mcecc SpecificationsCycle Types ECCDouble Bit Error Cycle Type = Burst Read or Non-Burst Read Error ReportingSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Double Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = Non-Burst WriteTriple or Greater Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = ScrubDouble Bit Error Cycle Type = Scrub Error LoggingTriple or Greater Bit Error Cycle Type = Scrub ScrubArbitration Chip DefaultsRefresh Programming Model Mcecc Base Address = $FFF43000 1st $FFF43100 2nd Mcecc Internal Register Memory Map, PartRegister Offset NameBase BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address D31 D30 D29 D28 D27 D26 D25 D24 Register Bit NamesScrub SAC7 SAC6 SAC5 SAC4 Addr Cntr 1st $FFF43000/2nd $FFF43100 8-bits MSIZ2-MSIZ0 Memory Configuration RegisterRB4 Read Bit 4 is a read only bit that is always Dummy RegisterRB3 Read Bit 3 is a read only bit that is always Bit assignments for the Base Address Register are Base Address RegisterDifference from MEMC040 none RWB3 Read/Write Bit 3 is a general purpose read/write bit Bit assignments for the Dram Control Register areRWB5 Read/Write Bit 5 is a general purpose read/write bit Bclk Frequency Register Data Control Register Mcecc Scrub Control Register This register contains bits 7-0 of the Scrub Period Register Scrub Period Register BitsSTOFF2-STOFF0 Chip Prescaler CounterScrub Time On/Time Off Register Scrubber Time On STON2-STON0Scrubber Time Off Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF4304C/2nd $FFF4314C 8-bits Error Logger Register Error Address Bits 1st $FFF43064/2nd $FFF43164 8-bits RSIZ2-RSIZ0 Error Syndrome RegisterDefaults Register Register Base Address SELI1, SELI0Dram Array Size Nocache RESST2-RESST0Initialization Mcecc Syndrome Decode Bank in Error Bit in Error Syndrome CodeBank C Bank a Mcecc Document Title Motorola Publication Number Motorola Computer Group DocumentsTable A-2. Manufacturers’ Documents Literature UpdatesManufacturers’ Documents Table A-2. Manufacturers’ Documents Related Documentation VMEchip2 Tick Timer 1 Periodic Interrupt Example BUsing Interrupts on the MVME172Refer to the Vector Base Register Step Register and Address Action and ReferenceUsing Interrupts on the MVME172 Page Index IN-2 DMA Gcsr Lanc IN-6 MPU SCC Scsi Mcecc IN-10 IN-11 Index MVME172 MVME172 Programmer’s Reference Guide