Motorola MVME172 manual IP2 Chip Clock Cycles

4

IP2 Chip

Table 4-1. IP2 Chip Clock Cycles

Bus Frequency		Period and Bandwidth to 32-Bit IP Space
MC68060	IP	Back to Back	Four Cycle	Single Cycle
		Examine	DMA Burst	DMA
		(Note 1)	(Note 2)	(Note 3)
25 MHz	8 MHz	4 IP clocks	10 IP clocks	4 IP clocks
		8 MB/sec	12.8 MB/sec	8 MB/sec
32 MHz	8 MHz	3 IP clocks	10 IP clocks	4 IP clocks
		10.6 MB/sec	12.8 MB/sec	8 MB/sec
32 MHz	32 MHz	6 IP clocks	12 IP clocks	6 IP clocks
	(Note 5)	21 MB/sec	42 MB/sec	21 MB/sec
			(Note 4)

Notes 1. This column is a measure of IndustryPack bandwidth for back to back cycles for a local bus master which is accessing a memory or I/O space location on an IndustryPack. It assumes a zero wait state acknowledge reply from the IndustryPack.

2.This column is a measure of IndustryPack bandwidth for DMA burst cycles between a local bus slave and a memory or I/O space location on an IndustryPack. It assumes a zero wait state acknowledge reply from the IndustryPack.

3.This column is a measure of IndustryPack bandwidth for DMA single cycles between a local bus slave and a memory or I/O space location on an IndustryPack. It assumes a zero wait state acknowledge reply from the IndustryPack.

4.Burst mode sDMA is not supported when both bus frequencies are 32 MHz.

5.Because the specified band width assumes a zero wait state IndustryPack cycle, it would be difficult to achieve the stated bandwidths for an IP bus frequency of 32 MHz.

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