Motorola MVME172 manual 53C710 Scsi Controller Interface, Sram Memory Controller, Lanc Interrupt

Functional Description

LANC Interrupt

The MC2 chip provides an interrupt control register for normal LANC termination and another register for bus error termination of LANC operation. The MC2 chip requests an interrupt at the level programmed in the LANC interrupt control registers if the interrupt is enabled and a positive edge is detected on the 82596CA INT* pin or if the LANC bus error condition is detected.

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53C710 SCSI Controller Interface

The MC2 chip provides a map decoder and an interrupt handler for the NCR 53C710 SCSI I/O Processor. The base address for the 53C710 is $FFF47000. The MC2 chip requests an interrupt at the level programmed in the SCSI interrupt control register if the interrupt is enabled and a low level is detected on the 53C710 IRQ* pin.

SRAM Memory Controller

The SRAM base address and size are programmable. The SRAM controller is designed to operate with 100 ns devices. The size of the SRAM is initialized in the DRAM/SRAM Options Register when the MVME172 is reset. SRAM performance at 25 MHz is 5,3,3,3 for read and write cycle. SRAM performance at 33 MHz is 6,4,4,4 for read cycles and 6,3,3,3 for write cycles.

NON-ECC DRAM Memory Controller

When the DRAM is non-ECC, the MC2 chip ASIC determines the DRAM performance. This section describes the DRAM options for that case.

The DRAM base address and array size are programmable. The DRAM is configured as an interleaved array if the size is 16MBytes and non interleaved if the size is 4 or 8 MBytes.

Parity checking and parity exception action is also programmable. The DRAM array size and DRAM device size is initialized in the DRAM/SRAM Options Register.

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