Motorola MVME172 manual Btd

	Programming Model
BTD	Setting BTD (bus turn around delay) to a one will insert
	one inactive clock period following a read cycle on the IP
	bus. This idle cycle is to eliminate bus contention which
	would occur if the time to assert a valid address by the IP2
	chip is less than the time required by the Industry Pack to
	put the bus in a high impedance state following the read
	cycle. The IP2 chip will drive the bus valid following the
	positive edge of the IP clock in typically seven
	nanoseconds, and worse case in 15. Note that
	IndustryPack modules which were designed to meet the
	0.7 or earlier revision of the GreenSprings IndustryPack
	Specification were allowed 40 ns to three-state the bus
	following a read cycle. The state of BTD affects IP bus
	cycles which are a result of the DMA function because
	they are the only cycles which can occur back to back.
	When BTD is set to a zero, the IndustryPack interface will
	start the next cycle as soon as possible.

Note The default BTD setting is to insert the additional one clock period delay between read cycles.

WIDTH1, The IP2 chip assumes the memory space data-bus

WIDTH0 width of each of IP_a, IP_b, IP_c, and IP_d to be the value decoded from its control bits WIDTH1 and WIDTH0. Note that the width bits control the assumed memory width for the load-stored (programmed I/O) data path. There is a similar set of bits for the DMA logic memory width control. The following table shows widths inferred by these bits. When a double size IndustryPack is used in ab, then IP_a should be programmed for 32 bit width, and the WIDTH and MEN control bits in the IP_b General Control Register should be cleared. When a double size IndustryPack is used at cd, then IP_c should both be programmed for 32 bit width, and the WIDTH and MEN control bits in the IP_d General Control Register should be cleared.

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