Motorola MVME172 manual Dhb, Robn

2

VMEchip2

		DHB		When this bit is high, the VMEbus has been acquired in
				response to the DWB bit being set. When the DWB bit is
				cleared, this bit is cleared.
		ROBN		When this bit is high, the VMEbus arbiter operates in the
				round robin mode. When this bit is low, the arbiter
				operates in the priority mode.
DMAC Control Register 1 (bits 0-7)
	ADR/SIZ				$FFF40030 (8 bits of 32)
	BIT	7	6		5	4	3	2	1	0
	NAME	DHALT	DEN		DTBL	DFAIR	DRELM		DREQL
	OPER	S	S		R/W	R/W	R/W		R/W
	RESET	0 PS	0 PS		0 PS	0 PS	0 PS		0 PS

This control register is loaded by the processor; it is not modified when the DMAC loads new values from the command packet.

DREQL These bits define the VMEbus request level for the DMAC requester. The request is only changed when the VMEchip2 is bus master. The VMEchip2 always requests at the old level until it becomes bus master and the new level takes effect. If the VMEchip2 is bus master when the level is changed, the new level does not take effect until the bus has been released and re-requested at the old level. The requester always requests the VMEbus at level 3 the first time following a SYSRESET.

0VMEbus request level 0

1VMEbus request level 1

2VMEbus request level 2

3VMEbus request level 3

DRELM These bits define the VMEbus release mode for the DMAC requester. The DMAC always releases the bus when the FIFO is full (VMEbus to local bus) or empty (local bus to VMEbus).

0Release when the time on timer has expired and a BRx* signal is active on the VMEbus.

1Release when the time on timer has expired.

2Release when a BRx* signal is active on the

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