VME Embedded Controller Programmer’s Reference Guide
MVME172
Restricted Rights Legend
Preface
Recent Updates
Page
Page
Contents
VMEchip2
Page
Page
MC2 Chip
Xii
IP2 Chip
Chapter Mcecc
Index
Figures
Xvii
Xviii
Overview
Introduction
Board Description and Memory Maps
MVME172 Features Summary
Requirements
Fuses LAN power SCON, LAN, Fuse LAN power
Feature 200/300-Series
No-VMEbus-Interface Option
Block Diagrams
Functional Description
300-Series MVME172 Block Diagram
500-Series MVME172
Block Diagram
VMEchip2 MC2 Chip Address Bit #
Redundant Functions in the VMEchip2 and MC2 Chip
Normal Address Range
Memory Maps
VMEbus Interface and VMEchip2
Local Bus Memory Map
300-Series MVME172 Local Bus Memory Map
Memory Maps
Devices Port Software Address Range
Cache Accessed Width Inhibit
500-Series MVME172 Local Bus Memory Map
Memory Maps
300-Series MVME172 Local I/O Devices Memory Map
Address Range Devices Accessed Port Size Width
$FFFBC000 $FFFBC01F
$FFFBC800 $FFFBC81F
Memory Maps
Address Range Device Port Size Width
500-Series MVME172 Local I/O Devices Memory Map
2KB $FFFBC800 $FFFBC81F
Board Description and Memory Maps
Tables 1-7 through 1-17 give the detailed memory maps for
Detailed I/O Memory Maps
Offset
VMEchip2 Memory Map Sheet 1
This sheet begins on facing
PRE
VMEchip2 Memory Map Sheet 2
Compare Register Counter Overflow
Offsets Bit Numbers
VMEchip2 Memory Map Sheet 3
Offset D31-D24 D23-D16 D15-D8 D7-D0
MC2 Chip Register Map
MC2 Chip Base Address = $FFF42000
Address Range Selected Device Port Width Size
IP2 Chip Overall Memory Map
IP2 Chip Base Address = $FFFBC000
10. IP2 Chip Memory Map Control and Status Registers
DMA
Dlbe
Chani TBL
$51 DMAc INT
Dlbe Ipend Chani TBL Ipto Done
Mcecc Base Address = $FFF43000 1st $FFF43100 2nd
11. Mcecc Internal Register Memory Map
Name D31 D30 D29 D28 D27 D26 D25 D24
Z85230 SCC Register Address
12. Z85230 SCC Register Addresses
13 CA Ethernet LAN Memory Map
14 C710 Scsi Memory Map
Address Range Description Size Bytes
BBRAM/TOD Clock Memory Map
15. MK48T58 BBRAM/TOD Clock Memory Map
Local Scsi ID
16. Bbram Configuration Area Memory Map
Address Data Bits Function
17. TOD Clock Memory Map
FT = Frequency Test x = Must be set to
Ecc1memserial
12 characters are followed by four blanks
3992B03A
Interrupt Acknowledge Map
VMEbus Memory Map
VMEbus Short I/O Memory Map
VMEbus Accesses to the Local Bus
Software Support Considerations
Interrupts
Local Bus Time-out
Cache Coherency
Sources of Local Berr
VMEbus Berr
VMEbus Access Time-out
Local Dram Parity Error
Bus Error Processing
MPU Parity Error
Description of Error Conditions on the MVME172
MPU Local Bus Time-out
MPU Off-board Error
MPU TEA Cause Unidentified
Dmac Parity Error
Dmac VMEbus Error
Dmac LTO Error
Dmac Off-board Error
Dmac TEA Cause Unidentified
LAN Parity Error
LAN LTO Error
LAN Off-Board Error
Scsi LTO Error
Scsi Parity Error
Scsi Off-Board Error
Example of the Proper Use of Bus Timers
MVME172 MC68060 Indivisible Cycles
Illegal Access to IP Modules from External VMEbus Masters
Page
VMEchip2
Summary of Major Features
VMEchip2
Introduction
Local Bus to VMEbus Interface
Functional Blocks
VMEchip2 Block Diagram
VMEchip2
Local Bus to VMEbus Requester
VMEchip2
Functional Blocks
VMEbus to Local Bus Interface
Local Bus to VMEbus DMA Controller
Functional Blocks
No Address Increment DMA Transfers
Dmac VMEbus Requester
Prescaler
Tick and Watchdog Timers
Watchdog Timer
Tick Timers
VMEbus Interrupter
Iack Daisy-Chain Driver
Bus Timer
VMEbus System Controller
Arbiter
Local Bus Interrupter and Interrupt Handler
Reset Driver
Functional Blocks
Global Control and Status Registers
Lcsr Programming Model
Summary of the Lcsr is shown in Table
VMEchip2 Memory Map Lcsr Summary Sheet 1
IO2 IO1
VMEchip2 Memory Map Lcsr Summary Sheet 2
IRQ7 IRQ6 IRQ5
Programming the VMEbus Slave Map Decoders
Lcsr Programming Model
VMEbus Slave Starting Address Register
VMEbus Slave Ending Address Register
VMEbus Slave Address Translation Address Offset Register
Segment Address Translation Size Select Value
VMEbus Slave Address Translation Select Register
$FFF4000C 16 bits
SNP2
VMEbus Slave Write Post and Snoop Control Register
WP2
BLK
VMEbus Slave Address Modifier Select Register
DAT
PGM
SUP
A32
USR
ADDER1
WP1
SNP1
Cycles
When this bit is high, the first map decoder responds to
Block access cycles
A24 access cycles
Bit is low, the first map decoder does not respond to
A32 access cycles
VMEbus supervisory access cycles. When this bit is low
Programming the Local Bus to VMEbus Map Decoders
VMEchip2
Local Bus Slave VMEbus Master Ending Address Register
Local Bus Slave VMEbus Master Starting Address Register
$FFF4001C 16 bits
$FFF40024 16 bits
D16
Local Bus Slave VMEbus Master Attribute Register
Decoder 3. Because the local bus to VMEbus interface
Segment defined by map decoder 3. When this bit is
Not support block transfers, the block transfer address
Segment defined by map decoder 2. When this bit is
Bus map decoder
Decoder 2. Since the local bus to VMEbus interface does
Decoder 1. Because the local bus to VMEbus interface
Segment defined by map decoder 1. When this bit is
VMEbus Slave Gcsr Group Address Register
VMEbus Slave Gcsr Board Address Register
EN3
Local Bus to VMEbus Enable Control Register
EN1
EN2
Local Bus to VMEbus I/O Control Register
I2EN
I2WP
Programming the VMEchip2 DMA Controller
Entry Function
Dmac Command Table Format
Dmac Registers
ROM0
Prom Decoder, Sram and DMA Control Register
Srams
Tblsc
Lvfair
Local Bus to VMEbus Requester Control Register
Lvreql
Lvrwd
Robn
DHB
Dhalt
Dfair
Dtbl
DEN
SNP
Tvme
Linc
Vinc
VME AM
Dmac VMEbus Address Counter
Dmac Local Bus Address Counter
Dmac VMEbus Address Counter
Dmac Byte Counter
Table Address Counter
VMEbus Interrupter Control Register
IRQ1S
Irql
Irqs
Irqc
MPU Status and DMA Interrupt Count Register
VMEbus Interrupter Vector Register
TBL
Dmac Status Register
Done
VME
VMEbus Arbiter Time-out Control Register
Programming the Tick and Watchdog Timers
Time on
Vgto
Vato
Lbto
Prescaler register = 256 B clock MHz
Prescaler Control Register
Tick timer 1 Compare Register
Tick Timer 1 Compare Register
Tick Timer 1 Counter
Tick timer 2 Counter
Tick Timer 2 Compare Register
Tick Timer 2 Counter
Board Control Register
Watchdog Timer Control Register
Tick Timer 2 Control Register
Prescaler Counter
Tick Timer 1 Control Register
Programming the Local Bus Interrupter
Interrupt Vector Priority for Simultaneous Interrupts
Local Bus Interrupter Summary
Dmac
Local Bus Interrupter Status Register bits
SIG1
LM0
LM1
SIG0
SW3
SW0
SW1
SW2
VME4
VME1
VME2
VME3
Local Bus Interrupter Enable Register bits
ESIG1
ELM0
ELM1
ESIG0
ESW3
ESW0
ESW1
ESW2
EIRQ4
EIRQ1
EIRQ2
EIRQ3
Software Interrupt Set Register bits
Interrupt Clear Register bits
Interrupt Level Register 1 bits
Sysf Level WPE Level
Interrupt Level Register 2 bits
SIG3 Level SIG2 Level
Interrupt Level Register 3 bits
SW5 Level SW4 Level
Interrupt Level Register 4 bits
VIRQ6 VIRQ5 Level
VBR
Vector Base Register
Control Register
Connects to pin 18 of the Remote Status and Control
Connects to pin 16 of the Remote Status and Control
Connects to pin 17 of the Remote Status and Control
Enint
Miscellaneous Control Register
100 Computer Group Literature Center Web Site
Gcsr Programming Model
102 Computer Group Literature Center Web Site
Gcsr Programming Model
Programming the Gcsr
Local Bus
Shows a summary of the Gcsr
VMEchip2 Memory Map Gcsr Summary
VMEchip2 LM/SIG Register
VMEchip2 Revision Register
VMEchip2 ID Register
LM2
RST
LM3
VMEchip2 Board Status/Control Register
ISF
General Purpose Register
Local Bus $FFF40110/VMEbus $XXY8 16 bits
Local Bus $FFF40118/VMEbus $XXYC 16 bits
MC2 Chip
Flash and Prom Interface
MC2 Chip Initialization
MPU Port and MPU Channel Attention
Bbram Interface
82596CA LAN Interface
MC68060-Bus Master Support for 82596CA
Lanc Bus Error
Lanc Interrupt
53C710 Scsi Controller Interface
Sram Memory Controller
NON-ECC Dram Memory Controller
Clock Budget Operating Conditions
Z85230 SCC Interface
Dram Performance
Address Range SCC Device Number
Tick Timers
Memory Map of the MC2 Chip Registers
Watchdog Timer
Local Bus Timer
Memory Map of the MC2 Chip Registers
Programming Model
MC2 Chip Revision Register
MC2 Chip ID Register
General Control Register
SCCIT10 Number of Z85230s
Interrupt Vector Base Register
Interrupt Source IV3-IV0 Daisy Chain Priority
Interrupt Vector Base Register Encoding Priority
Tick Timer 1 and 2 Compare and Counter Registers
Programming the Tick Timers
Tick Timer 2 Compare Register
Tick Timer 1 Compare Register
Tick Timer 1 Counter
LSB Prescaler Count Register
Tick Timer 2 Counter
Tick Timer 1 and 2 Control Registers
Prescaler Clock Adjust Register
OVF3-OVF0
Tick Timer 2 Control Register
Tick Timer 1 Control Register
Tick Timer 2 Interrupt Control Register
Tick Timer Interrupt Control Registers
Tick Timer 4 Interrupt Control Register
Tick Timer 3 Interrupt Control Register
Tick Timer 1 Interrupt Control Register
IEN
Dram Parity Error Interrupt Control Register
IL2-IL0
Iclr
SCC Interrupt Control Register
Tick Timer 3 Control Register
Tick Timer 3 and 4 Control Registers
Tick Timer 4 Control Register
Dram Space Base Address Register
Dram and Sram Memory Controller Registers
Dram Space Size Register
Sram Space Base Address Register
DZ2 DZ0 Memory Size
Dram Size Control Bit Encoding
DRAM/SRAM Options Register
28F020 256K x 8 Flash memory devices are used
Sram Size Control Bit Encoding
F0 set to a 0 indicates that one 28F016SA 2M x 8 Flash
Memory device is used. F0 set to a 1 indicates that four
SZ1 SZ0 Memory Size
Sram Space Size Register
LTO, EXT, Prty
Lanc Error Status Register
Plty
82596CA Lanc Interrupt Control Register
Lanc Bus Error Interrupt Control Register
General Purpose Inputs Register
Scsi Error Status Register
V11
MVME172 Version Register
Scsi Interrupt Control Register
Tick Timer 3 Counter
Tick Timer 3 and 4 Compare and Counter Registers
Tick Timer 3 Compare Register
Bus Clock Register
Tick Timer 4 Compare Register
Tick Timer 4 Counter
At 25 MHz where N = At 33 MHz where N =
Prom Access Time Control Register
ET2 Prom Access = N
FT2 Flash Access = N
Flash Access Time Control Register
Abort Switch Interrupt Control Register
Reset Switch Control Register
Watchdog Timer Control Register
Bit Time-out Encoding
Access and Watchdog Time Base Select Register
Wdto These bits define the watchdog time-out period
Dram Control Register
Alternate
MPU Status Register
PAREN-PARINT
Clock tick
Programming Model
Bit Prescaler Count Register
IP2 Chip
General Description
Local Bus to IndustryPack DMA Controllers
IP2 Chip
Clocking Environments and Performance
IP2 Chip Clock Cycles
Error Reporting as a Local Bus Master
Error Reporting
Following paragraphs describe the IP2 chip error reporting
Error Reporting as a Local Bus Slave
IndustryPack Error Reporting
Overall Memory Map
This status bit is cleared by writing a one to it
This bit is readable and writable
Register Register Name Register Bit Names Offset
IP2 Chip Memory Map Control and Status Registers
DMA Rotat
Dint Dien Diclr
Chani TBL
$5B DMAc LB
Dmac for
Chip Revision Register
Chip ID Register
Vector Base Register
IV2-0 Interrupt Source
IPa, IPb, IPc, IPd Memory Base Address Registers
IPb Memory Base Address Registers
IPa or Double Size IPab Memory Base Address Registers
IPd Memory Base Address Registers
IPa, IPb, IPc, IPd Memory Size Registers
IPc or Double Size IPcd Memory Base Address Registers
Not used on 200/300-Series MVME172
BIT NAME$0C
When this bit is high, an interrupt is being generated for
Corresponding INT status bit. In level-sensitive mode
When IEN is set, the interrupt is enabled. When IEN is
Cleared, the interrupt is disabled
MEN
IPa, IPb, IPc, and IPd General Control Registers
BTD
Memory Space Data Width
DERR
AERR
BERR
CERR
IP32
Setting IP32 to a one enables the IndustryPack bus to
Setting it to a zero will enable 8 MHz operation. In this
IP Clock Register
Local bus. If Rotat is set to a one, the priority is fixed
Where each Dmac has equal access to the MC68060
DMA Arbitration Control Register
RES
IP Reset Register
Programming the DMA Controllers
Control Word Byte Count
DMA Control and Status Register Set Definition
DMA Enable Function
Ipto
DMA Status Register
Dint
Ipend
DIL2-DIL0
Dien
DEN
DMA Control Register
Adma
Ento
Toip
DMA Local Bus Address Counter
Dmaei
DMA Byte Counter
DMA IndustryPack Address Counter
DMA Table Address Counter
IRE
Programming the Programmable Clock
Programmable Clock Interrupt Control Register
IL2-0
CLR
Programmable Clock General Control Register
PS2-0
PLS
Programmable Clock Timer Register
Comments
Local Bus to IndustryPack Addressing
Bit Memory Space
Local Bus to IndustryPack Addressing
$00FFFFFB $7FFFFD
IPA6-0 Comments
IPa I/O Space
IPab I/O Space
IPA5-0 Comments
IPa ID Space
This section shows data routing from an IP to the local bus
Memory Space Accesses
IP to Local Bus Data Routing
IP to Local Bus Data Routing
Space Lbsize LBA IPA
ID Space Accesses
Mcecc
Features
Performance
Descriptions Specifications
Mcecc Specifications
Cycle Types
ECC
Double Bit Error Cycle Type = Burst Read or Non-Burst Read
Error Reporting
Single Bit Error Cycle Type = Burst Read or Non-Burst Read
Single Bit Error Cycle Type = Scrub
Single Bit Error Cycle Type = Non-Burst Write
Double Bit Error Cycle Type = Non-Burst Write
Triple or Greater Bit Error Cycle Type = Non-Burst Write
Scrub
Error Logging
Double Bit Error Cycle Type = Scrub
Triple or Greater Bit Error Cycle Type = Scrub
Arbitration
Chip Defaults
Refresh
Programming Model
Offset Name
Mcecc Internal Register Memory Map, Part
Mcecc Base Address = $FFF43000 1st $FFF43100 2nd
Register
Base BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address
D31 D30 D29 D28 D27 D26 D25 D24
Register Bit Names
Scrub SAC7 SAC6 SAC5 SAC4 Addr Cntr
1st $FFF43000/2nd $FFF43100 8-bits
MSIZ2-MSIZ0
Memory Configuration Register
RB4 Read Bit 4 is a read only bit that is always
Dummy Register
RB3 Read Bit 3 is a read only bit that is always
Bit assignments for the Base Address Register are
Base Address Register
Difference from MEMC040 none
RWB3 Read/Write Bit 3 is a general purpose read/write bit
Bit assignments for the Dram Control Register are
RWB5 Read/Write Bit 5 is a general purpose read/write bit
Bclk Frequency Register
Data Control Register
Mcecc
Scrub Control Register
This register contains bits 7-0 of the Scrub Period Register
Scrub Period Register Bits
STOFF2-STOFF0
Chip Prescaler Counter
Scrub Time On/Time Off Register
Scrubber Time On
STON2-STON0
Scrubber Time Off
Scrub Prescaler Counter Bits
Scrub Timer Counter Bits
Scrub Address Counter Bits
1st $FFF4304C/2nd $FFF4314C 8-bits
Error Logger Register
Error Address Bits
1st $FFF43064/2nd $FFF43164 8-bits
RSIZ2-RSIZ0
Error Syndrome Register
Defaults Register
Register Base Address
SELI1, SELI0
Dram Array Size
Nocache
RESST2-RESST0
Initialization
Mcecc
Syndrome Decode
Bank in Error Bit in Error Syndrome Code
Bank C
Bank a
Mcecc
Document Title Motorola Publication Number
Motorola Computer Group Documents
Table A-2. Manufacturers’ Documents
Literature Updates
Manufacturers’ Documents
Table A-2. Manufacturers’ Documents
Related Documentation
VMEchip2 Tick Timer 1 Periodic Interrupt Example
BUsing Interrupts on the MVME172
Refer to the Vector Base Register
Step Register and Address Action and Reference
Using Interrupts on the MVME172
Page
Index
IN-2
DMA
Gcsr
Lanc
IN-6
MPU
SCC
Scsi Mcecc
IN-10
IN-11
Index
MVME172
MVME172 Programmer’s Reference Guide
