Scrub Control Register | Motorola MVME172 specs

Programming Model

Scrub Control Register

ADR/SIZ		1st $FFF43024/2nd $FFF43124 (8-bits)

BIT	31	30	29	28	27	26		25	24

NAME	RACODE	RADATA	HITDIS	SCRB	SCRBEN	0		SBEIEN	IDIS

OPER	R/W	R/W	R/W	R	R/W	R		R/W	R/W

RESET	V PLS	0 PLS	V PLS	0 PLS	0 PLS	X		0 PLS	0 PLS

IDIS When cleared, the Image DISable bit allows writes to the upper MCECC control registers to duplicate the data to the lower MCECC control registers. When IDIS is set, the lower MCECC control registers are written separately by the data on D00-D16. IDIS should only be set for test purposes.

SBEIEN Setting SBEIEN causes the logging of a single bit error to create a true pulse on the INT signal pin.

SCRBEN This control bit enables the scrubber to operate. When SCRBEN is set, the MCECC immediately performs a scrub of the entire DRAM array. When the scrub is complete, if software has cleared SCRBEN, then scrubbing is not done again, until software sets the SCRBEN bit. If software has not cleared the SCRBEN bit, then when the amount of time indicated in the Scrub Period (SBPD) Register expires, the MCECC scrubs the DRAM array again. It continues to perform scrubs of the entire DRAM array at the frequency indicated in the SBPD Register. The scrubber does not start a new scrub once the SCRBEN bit is cleared. The time between scrubs is approximately two seconds times the value stored in the SBPD Register. Note that power-up, local, or software reset stops the scrubber.

SCRB This status bit reflects the state of the scrubber. When the scrubber is in the process of doing a scrub, this bit is set. When the scrubber is between scrubs, this bit is cleared.

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Motorola MVME172 manual Scrub Control Register

Contents

VME Embedded Controller Programmer’s Reference Guide MVME172 Restricted Rights Legend Preface Recent Updates Page Page Contents VMEchip2 Page Page MC2 Chip Xii IP2 Chip Chapter Mcecc Index Figures Xvii Xviii Overview Introduction Board Description and Memory Maps MVME172 Features Summary Feature 200/300-Series Fuses LAN power SCON, LAN, Fuse LAN powerRequirements Functional Description Block DiagramsNo-VMEbus-Interface Option 300-Series MVME172 Block Diagram 500-Series MVME172 Block Diagram VMEchip2 MC2 Chip Address Bit # Redundant Functions in the VMEchip2 and MC2 Chip VMEbus Interface and VMEchip2 Memory MapsLocal Bus Memory Map Normal Address Range 300-Series MVME172 Local Bus Memory Map Memory Maps 500-Series MVME172 Local Bus Memory Map Cache Accessed Width InhibitDevices Port Software Address Range Memory Maps 300-Series MVME172 Local I/O Devices Memory Map Address Range Devices Accessed Port Size Width $FFFBC000 $FFFBC01F $FFFBC800 $FFFBC81F Memory Maps Address Range Device Port Size Width 500-Series MVME172 Local I/O Devices Memory Map 2KB $FFFBC800 $FFFBC81F Board Description and Memory Maps Tables 1-7 through 1-17 give the detailed memory maps for Detailed I/O Memory Maps Offset VMEchip2 Memory Map Sheet 1 This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2 Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3 MC2 Chip Base Address = $FFF42000 MC2 Chip Register MapOffset D31-D24 D23-D16 D15-D8 D7-D0 Address Range Selected Device Port Width Size IP2 Chip Overall Memory Map IP2 Chip Base Address = $FFFBC000 10. IP2 Chip Memory Map Control and Status Registers DMA Dlbe Chani TBL $51 DMAc INT Dlbe Ipend Chani TBL Ipto Done Mcecc Base Address = $FFF43000 1st $FFF43100 2nd 11. Mcecc Internal Register Memory Map Name D31 D30 D29 D28 D27 D26 D25 D24 Z85230 SCC Register Address 12. Z85230 SCC Register Addresses 13 CA Ethernet LAN Memory Map 14 C710 Scsi Memory Map 15. MK48T58 BBRAM/TOD Clock Memory Map BBRAM/TOD Clock Memory MapAddress Range Description Size Bytes Local Scsi ID 16. Bbram Configuration Area Memory Map FT = Frequency Test x = Must be set to 17. TOD Clock Memory MapAddress Data Bits Function Ecc1memserial 12 characters are followed by four blanks 3992B03A Interrupt Acknowledge Map VMEbus Memory Map Software Support Considerations VMEbus Accesses to the Local BusInterrupts VMEbus Short I/O Memory Map Sources of Local Berr Cache CoherencyLocal Bus Time-out Local Dram Parity Error VMEbus Access Time-outBus Error Processing VMEbus Berr MPU Parity Error Description of Error Conditions on the MVME172 MPU TEA Cause Unidentified MPU Off-board ErrorMPU Local Bus Time-out Dmac Parity Error Dmac VMEbus Error Dmac LTO Error Dmac Off-board Error Dmac TEA Cause Unidentified LAN Parity Error LAN LTO Error LAN Off-Board Error Scsi Off-Board Error Scsi Parity ErrorScsi LTO Error Example of the Proper Use of Bus Timers MVME172 MC68060 Indivisible Cycles Illegal Access to IP Modules from External VMEbus Masters Page VMEchip2 Summary of Major Features VMEchip2 Introduction Local Bus to VMEbus Interface Functional Blocks VMEchip2 Block Diagram VMEchip2 Local Bus to VMEbus Requester VMEchip2 Functional Blocks VMEbus to Local Bus Interface Local Bus to VMEbus DMA Controller Functional Blocks No Address Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog Timers Watchdog Timer Tick Timers VMEbus Interrupter VMEbus System Controller Bus TimerArbiter Iack Daisy-Chain Driver Local Bus Interrupter and Interrupt Handler Reset Driver Functional Blocks Global Control and Status Registers Lcsr Programming Model Summary of the Lcsr is shown in Table VMEchip2 Memory Map Lcsr Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map Lcsr Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address Register VMEbus Slave Address Translation Address Offset Register Segment Address Translation Size Select Value VMEbus Slave Address Translation Select Register $FFF4000C 16 bits WP2 VMEbus Slave Write Post and Snoop Control RegisterSNP2 DAT VMEbus Slave Address Modifier Select RegisterPGM BLK USR A32SUP SNP1 WP1ADDER1 Block access cycles When this bit is high, the first map decoder responds toA24 access cycles Cycles VMEbus supervisory access cycles. When this bit is low A32 access cyclesProgramming the Local Bus to VMEbus Map Decoders Bit is low, the first map decoder does not respond to VMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits D16 Local Bus Slave VMEbus Master Attribute Register Decoder 3. Because the local bus to VMEbus interface Segment defined by map decoder 3. When this bit is Bus map decoder Segment defined by map decoder 2. When this bit isDecoder 2. Since the local bus to VMEbus interface does Not support block transfers, the block transfer address Decoder 1. Because the local bus to VMEbus interface Segment defined by map decoder 1. When this bit is VMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN1 Local Bus to VMEbus Enable Control RegisterEN2 EN3 Local Bus to VMEbus I/O Control Register I2EN I2WP Programming the VMEchip2 DMA Controller Dmac Registers Dmac Command Table FormatEntry Function Srams Prom Decoder, Sram and DMA Control RegisterTblsc ROM0 Lvreql Local Bus to VMEbus Requester Control RegisterLvrwd Lvfair Robn DHB Dtbl DfairDEN Dhalt Linc TvmeVinc SNP VME AM Dmac VMEbus Address Counter Dmac Local Bus Address CounterDmac VMEbus Address Counter VMEbus Interrupter Control Register Table Address CounterDmac Byte Counter Irqs IrqlIrqc IRQ1S MPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector Register Done Dmac Status RegisterVME TBL VMEbus Arbiter Time-out Control Register Programming the Tick and Watchdog Timers Time on Vgto Vato Lbto Prescaler register = 256 B clock MHz Prescaler Control Register Tick Timer 1 Counter Tick Timer 1 Compare RegisterTick timer 1 Compare Register Tick Timer 2 Counter Tick Timer 2 Compare RegisterTick timer 2 Counter Board Control Register Watchdog Timer Control Register Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control Register Programming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter Summary Dmac Local Bus Interrupter Status Register bits LM1 LM0SIG0 SIG1 SW1 SW0SW2 SW3 VME2 VME1VME3 VME4 Local Bus Interrupter Enable Register bits ELM1 ELM0ESIG0 ESIG1 ESW1 ESW0ESW2 ESW3 EIRQ2 EIRQ1EIRQ3 EIRQ4 Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits Sysf Level WPE Level Interrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ6 VIRQ5 Level VBR Vector Base Register Control Register Connects to pin 17 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Enint Miscellaneous Control Register 100 Computer Group Literature Center Web Site Gcsr Programming Model 102 Computer Group Literature Center Web Site Gcsr Programming Model Programming the Gcsr VMEchip2 Memory Map Gcsr Summary Shows a summary of the GcsrLocal Bus VMEchip2 ID Register VMEchip2 Revision RegisterVMEchip2 LM/SIG Register LM2 VMEchip2 Board Status/Control Register LM3ISF RST General Purpose Register Local Bus $FFF40110/VMEbus $XXY8 16 bits Local Bus $FFF40118/VMEbus $XXYC 16 bits MC2 Chip Flash and Prom Interface MC2 Chip Initialization 82596CA LAN Interface Bbram InterfaceMPU Port and MPU Channel Attention MC68060-Bus Master Support for 82596CA Lanc Bus Error Sram Memory Controller 53C710 Scsi Controller InterfaceNON-ECC Dram Memory Controller Lanc Interrupt Dram Performance Z85230 SCC InterfaceClock Budget Operating Conditions Address Range SCC Device Number Tick Timers Local Bus Timer Watchdog TimerMemory Map of the MC2 Chip Registers Memory Map of the MC2 Chip Registers Programming Model MC2 Chip Revision Register MC2 Chip ID Register General Control Register SCCIT10 Number of Z85230s Interrupt Vector Base Register Interrupt Source IV3-IV0 Daisy Chain Priority Interrupt Vector Base Register Encoding Priority Tick Timer 1 and 2 Compare and Counter Registers Programming the Tick Timers Tick Timer 1 Counter Tick Timer 1 Compare RegisterTick Timer 2 Compare Register LSB Prescaler Count Register Tick Timer 2 Counter Tick Timer 1 and 2 Control Registers Prescaler Clock Adjust Register Tick Timer 1 Control Register Tick Timer 2 Control RegisterOVF3-OVF0 Tick Timer 4 Interrupt Control Register Tick Timer Interrupt Control RegistersTick Timer 3 Interrupt Control Register Tick Timer 2 Interrupt Control Register Tick Timer 1 Interrupt Control Register IL2-IL0 Dram Parity Error Interrupt Control RegisterIclr IEN SCC Interrupt Control Register Tick Timer 4 Control Register Tick Timer 3 and 4 Control RegistersTick Timer 3 Control Register Dram Space Base Address Register Dram and Sram Memory Controller Registers Dram Space Size Register Sram Space Base Address Register DRAM/SRAM Options Register Dram Size Control Bit EncodingDZ2 DZ0 Memory Size F0 set to a 0 indicates that one 28F016SA 2M x 8 Flash Sram Size Control Bit EncodingMemory device is used. F0 set to a 1 indicates that four 28F020 256K x 8 Flash memory devices are used SZ1 SZ0 Memory Size Sram Space Size Register LTO, EXT, Prty Lanc Error Status Register Plty 82596CA Lanc Interrupt Control Register Lanc Bus Error Interrupt Control Register General Purpose Inputs Register Scsi Error Status Register V11 MVME172 Version Register Scsi Interrupt Control Register Tick Timer 3 Compare Register Tick Timer 3 and 4 Compare and Counter RegistersTick Timer 3 Counter Tick Timer 4 Counter Tick Timer 4 Compare RegisterBus Clock Register ET2 Prom Access = N Prom Access Time Control RegisterAt 25 MHz where N = At 33 MHz where N = FT2 Flash Access = N Flash Access Time Control Register Abort Switch Interrupt Control Register Reset Switch Control Register Watchdog Timer Control Register Wdto These bits define the watchdog time-out period Access and Watchdog Time Base Select RegisterBit Time-out Encoding Dram Control Register PAREN-PARINT MPU Status RegisterClock tick Alternate Programming Model Bit Prescaler Count Register IP2 Chip General Description Local Bus to IndustryPack DMA Controllers IP2 Chip Clocking Environments and Performance IP2 Chip Clock Cycles Following paragraphs describe the IP2 chip error reporting Error ReportingError Reporting as a Local Bus Slave Error Reporting as a Local Bus Master IndustryPack Error Reporting Overall Memory Map This status bit is cleared by writing a one to it This bit is readable and writable Register Register Name Register Bit Names Offset IP2 Chip Memory Map Control and Status Registers DMA Rotat Dint Dien Diclr Chani TBL $5B DMAc LB Dmac for Chip Revision Register Chip ID Register Vector Base Register IV2-0 Interrupt Source IPa, IPb, IPc, IPd Memory Base Address Registers IPb Memory Base Address Registers IPa or Double Size IPab Memory Base Address Registers IPc or Double Size IPcd Memory Base Address Registers IPa, IPb, IPc, IPd Memory Size RegistersNot used on 200/300-Series MVME172 IPd Memory Base Address Registers BIT NAME$0C When IEN is set, the interrupt is enabled. When IEN is Corresponding INT status bit. In level-sensitive modeCleared, the interrupt is disabled When this bit is high, an interrupt is being generated for MEN IPa, IPb, IPc, and IPd General Control Registers BTD Memory Space Data Width BERR AERRCERR DERR Setting it to a zero will enable 8 MHz operation. In this Setting IP32 to a one enables the IndustryPack bus toIP Clock Register IP32 DMA Arbitration Control Register Where each Dmac has equal access to the MC68060Local bus. If Rotat is set to a one, the priority is fixed RES IP Reset Register Programming the DMA Controllers Control Word Byte Count DMA Control and Status Register Set Definition DMA Enable Function Ipto DMA Status Register DIL2-DIL0 IpendDien Dint DEN DMA Control Register Adma Ento Toip DMA Local Bus Address Counter Dmaei DMA Byte Counter DMA IndustryPack Address Counter DMA Table Address Counter Programmable Clock Interrupt Control Register Programming the Programmable ClockIL2-0 IRE PS2-0 Programmable Clock General Control RegisterCLR PLS Programmable Clock Timer Register Bit Memory Space Local Bus to IndustryPack AddressingComments Local Bus to IndustryPack Addressing $00FFFFFB $7FFFFD IPA6-0 Comments IPa I/O Space IPab I/O Space IPA5-0 Comments IPa ID Space IP to Local Bus Data Routing Memory Space AccessesThis section shows data routing from an IP to the local bus IP to Local Bus Data Routing Space Lbsize LBA IPA ID Space Accesses Mcecc Features Performance Descriptions Specifications Mcecc Specifications Cycle Types ECC Single Bit Error Cycle Type = Burst Read or Non-Burst Read Error ReportingDouble Bit Error Cycle Type = Burst Read or Non-Burst Read Double Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = Non-Burst WriteTriple or Greater Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = Scrub Double Bit Error Cycle Type = Scrub Error LoggingTriple or Greater Bit Error Cycle Type = Scrub Scrub Refresh Chip DefaultsArbitration Programming Model Mcecc Base Address = $FFF43000 1st $FFF43100 2nd Mcecc Internal Register Memory Map, PartRegister Offset Name Base BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address D31 D30 D29 D28 D27 D26 D25 D24 Register Bit Names Scrub SAC7 SAC6 SAC5 SAC4 Addr Cntr 1st $FFF43000/2nd $FFF43100 8-bits MSIZ2-MSIZ0 Memory Configuration Register RB3 Read Bit 3 is a read only bit that is always Dummy RegisterRB4 Read Bit 4 is a read only bit that is always Difference from MEMC040 none Base Address RegisterBit assignments for the Base Address Register are RWB3 Read/Write Bit 3 is a general purpose read/write bit Bit assignments for the Dram Control Register are RWB5 Read/Write Bit 5 is a general purpose read/write bit Bclk Frequency Register Data Control Register Mcecc Scrub Control Register This register contains bits 7-0 of the Scrub Period Register Scrub Period Register Bits Scrub Time On/Time Off Register Chip Prescaler CounterSTOFF2-STOFF0 Scrubber Time Off STON2-STON0Scrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF4304C/2nd $FFF4314C 8-bits Error Logger Register Error Address Bits 1st $FFF43064/2nd $FFF43164 8-bits Defaults Register Error Syndrome RegisterRSIZ2-RSIZ0 Dram Array Size SELI1, SELI0Register Base Address Nocache RESST2-RESST0 Initialization Mcecc Syndrome Decode Bank in Error Bit in Error Syndrome Code Bank C Bank a Mcecc Document Title Motorola Publication Number Motorola Computer Group Documents Manufacturers’ Documents Literature UpdatesTable A-2. Manufacturers’ Documents Table A-2. Manufacturers’ Documents Related Documentation VMEchip2 Tick Timer 1 Periodic Interrupt Example BUsing Interrupts on the MVME172 Refer to the Vector Base Register Step Register and Address Action and Reference Using Interrupts on the MVME172 Page Index IN-2 DMA Gcsr Lanc IN-6 MPU SCC Scsi Mcecc IN-10 IN-11 Index MVME172 MVME172 Programmer’s Reference Guide