Motorola MVME172 manual Programming the DMA Controllers

Programming Model

Programming the DMA Controllers

The IP2 chip implements four DMA channels. They can operate in the standard or addressed mode. sDMA transfers must accommodate the I/O port width. If the port width is 16 bits, then the byte count must be even; if the width is 32 bits, then the byte count must be a multiple of four bytes. The IP address counter must be initialized to zero before an sDMA transfer is enabled. There are not any other restrictions placed on DMA operations.

Each DMAC has two modes of operation: command chaining, and direct. In the direct mode, the local bus address, the IndustryPack address, the byte count, and the control register of a DMAC are programmed and the DMAC is enabled. The DMAC transfers data, as programmed, until the byte count is zero, DMAEND is detected true as an input, or an error is detected. When the DMAC stops, the status bits in the DMAC status register are set and an interrupt is sent to the local bus master (if the DMACs interrupts are enabled). Multiple DMAC commands can be automatically invoked using the command chaining mode.

In the command chaining mode, a singly-linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands. The DMAC control register 1 is programmed and the DMAC is enabled. The DMAC executes commands from the list until all commands are executed or an error is detected. When the DMAC stops, the status bits are set in the DMAC status register and an interrupt is sent to the local bus master (if the DMAC interrupts are enabled). Additionally, when the DMAC finishes processing a command in the list, and interrupts are enabled for that command, the DMAC sends an interrupt to the local bus master if its interrupts are enabled.

Note that when the DMA register context is updated for the next command packet, a DMA function is used. The state of the snoop control signals for this DMA function is determined by the settings of jumper J26 (as is the state of the snoop control signals for all other DMA cycle types). Refer to the Hardware Preparation section of your MVME172 installation and use manual.

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