Initialization | Motorola MVME172 specification

Programming Model

initialized by power-up, soft, or local reset to match the NOCACHE bit in the reset serial bit stream. It should always be left at the default value of 1.

TVECT TVECT makes bidirectional signals work while running the vendors test vectors on this chip. It should be cleared for normal operation. It is initialized by power-up, soft, or local reset, to match the TVECT bit from the reset serial bit stream.

REFDIS When REFDIS is set, refreshing is disabled. This mode should only be used for testing, as DRAM must have refresh to operate correctly. REFDIS is initialized by power-up, soft, or local reset to match the REFDIS bit in the reset serial bit stream.

XY_FLIP When XY_FLIP is set, the opposite internal set of cache latches is selected. This bit should be used with caution and is for test vector coverage improvement.

FRC_OPN When FRC_OPN is set, the internal DRAM read latches are forced continuously open. This bit should be used with caution and is for test vector coverage improvement.

Initialization

Most DRAM vendors require that the DRAMs be subjected to some number of access cycles before the DRAMs are fully operational. The MCECC does not perform this automatically but depends on software to perform enough dummy accesses to DRAM to meet the requirement. The number of required cycles is less than 10. If there are multiple blocks of DRAM, software has to perform at least 10 accesses to each block.

The MCECC pair provides a fast zero fill capability. The sequence shown below performs such a zero fill. It zeros all of the DRAM controlled by this MCECC pair at the rate of 100 MB/second when the BCLK pin is

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Motorola MVME172 manual Initialization

Contents

VME Embedded Controller Programmer’s Reference Guide MVME172 Restricted Rights Legend Preface Recent Updates Page Page Contents VMEchip2 Page Page MC2 Chip Xii IP2 Chip Chapter Mcecc Index Figures Xvii Xviii Overview Introduction Board Description and Memory Maps MVME172 Features Summary Fuses LAN power SCON, LAN, Fuse LAN power Feature 200/300-SeriesRequirements Block Diagrams Functional DescriptionNo-VMEbus-Interface Option 300-Series MVME172 Block Diagram 500-Series MVME172 Block Diagram VMEchip2 MC2 Chip Address Bit # Redundant Functions in the VMEchip2 and MC2 Chip Normal Address Range Memory MapsVMEbus Interface and VMEchip2 Local Bus Memory Map 300-Series MVME172 Local Bus Memory Map Memory Maps Cache Accessed Width Inhibit 500-Series MVME172 Local Bus Memory MapDevices Port Software Address Range Memory Maps 300-Series MVME172 Local I/O Devices Memory Map Address Range Devices Accessed Port Size Width $FFFBC000 $FFFBC01F $FFFBC800 $FFFBC81F Memory Maps Address Range Device Port Size Width 500-Series MVME172 Local I/O Devices Memory Map 2KB $FFFBC800 $FFFBC81F Board Description and Memory Maps Tables 1-7 through 1-17 give the detailed memory maps for Detailed I/O Memory Maps Offset VMEchip2 Memory Map Sheet 1 This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2 Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3 MC2 Chip Register Map MC2 Chip Base Address = $FFF42000Offset D31-D24 D23-D16 D15-D8 D7-D0 Address Range Selected Device Port Width Size IP2 Chip Overall Memory Map IP2 Chip Base Address = $FFFBC000 10. IP2 Chip Memory Map Control and Status Registers DMA Dlbe Chani TBL $51 DMAc INT Dlbe Ipend Chani TBL Ipto Done Mcecc Base Address = $FFF43000 1st $FFF43100 2nd 11. Mcecc Internal Register Memory Map Name D31 D30 D29 D28 D27 D26 D25 D24 Z85230 SCC Register Address 12. Z85230 SCC Register Addresses 13 CA Ethernet LAN Memory Map 14 C710 Scsi Memory Map BBRAM/TOD Clock Memory Map 15. MK48T58 BBRAM/TOD Clock Memory MapAddress Range Description Size Bytes Local Scsi ID 16. Bbram Configuration Area Memory Map 17. TOD Clock Memory Map FT = Frequency Test x = Must be set toAddress Data Bits Function Ecc1memserial 12 characters are followed by four blanks 3992B03A Interrupt Acknowledge Map VMEbus Memory Map VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusSoftware Support Considerations Interrupts Cache Coherency Sources of Local BerrLocal Bus Time-out VMEbus Berr VMEbus Access Time-outLocal Dram Parity Error Bus Error Processing MPU Parity Error Description of Error Conditions on the MVME172 MPU Off-board Error MPU TEA Cause UnidentifiedMPU Local Bus Time-out Dmac Parity Error Dmac VMEbus Error Dmac LTO Error Dmac Off-board Error Dmac TEA Cause Unidentified LAN Parity Error LAN LTO Error LAN Off-Board Error Scsi Parity Error Scsi Off-Board ErrorScsi LTO Error Example of the Proper Use of Bus Timers MVME172 MC68060 Indivisible Cycles Illegal Access to IP Modules from External VMEbus Masters Page VMEchip2 Summary of Major Features VMEchip2 Introduction Local Bus to VMEbus Interface Functional Blocks VMEchip2 Block Diagram VMEchip2 Local Bus to VMEbus Requester VMEchip2 Functional Blocks VMEbus to Local Bus Interface Local Bus to VMEbus DMA Controller Functional Blocks No Address Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog Timers Watchdog Timer Tick Timers VMEbus Interrupter Iack Daisy-Chain Driver Bus TimerVMEbus System Controller Arbiter Local Bus Interrupter and Interrupt Handler Reset Driver Functional Blocks Global Control and Status Registers Lcsr Programming Model Summary of the Lcsr is shown in Table VMEchip2 Memory Map Lcsr Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map Lcsr Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address Register VMEbus Slave Address Translation Address Offset Register Segment Address Translation Size Select Value VMEbus Slave Address Translation Select Register $FFF4000C 16 bits VMEbus Slave Write Post and Snoop Control Register WP2SNP2 BLK VMEbus Slave Address Modifier Select RegisterDAT PGM A32 USRSUP WP1 SNP1ADDER1 Cycles When this bit is high, the first map decoder responds toBlock access cycles A24 access cycles Bit is low, the first map decoder does not respond to A32 access cyclesVMEbus supervisory access cycles. When this bit is low Programming the Local Bus to VMEbus Map Decoders VMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits D16 Local Bus Slave VMEbus Master Attribute Register Decoder 3. Because the local bus to VMEbus interface Segment defined by map decoder 3. When this bit is Not support block transfers, the block transfer address Segment defined by map decoder 2. When this bit isBus map decoder Decoder 2. Since the local bus to VMEbus interface does Decoder 1. Because the local bus to VMEbus interface Segment defined by map decoder 1. When this bit is VMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN3 Local Bus to VMEbus Enable Control RegisterEN1 EN2 Local Bus to VMEbus I/O Control Register I2EN I2WP Programming the VMEchip2 DMA Controller Dmac Command Table Format Dmac RegistersEntry Function ROM0 Prom Decoder, Sram and DMA Control RegisterSrams Tblsc Lvfair Local Bus to VMEbus Requester Control RegisterLvreql Lvrwd Robn DHB Dhalt DfairDtbl DEN SNP TvmeLinc Vinc VME AM Dmac Local Bus Address Counter Dmac VMEbus Address CounterDmac VMEbus Address Counter Table Address Counter VMEbus Interrupter Control RegisterDmac Byte Counter IRQ1S IrqlIrqs Irqc MPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector Register TBL Dmac Status RegisterDone VME VMEbus Arbiter Time-out Control Register Programming the Tick and Watchdog Timers Time on Vgto Vato Lbto Prescaler register = 256 B clock MHz Prescaler Control Register Tick Timer 1 Compare Register Tick Timer 1 CounterTick timer 1 Compare Register Tick Timer 2 Compare Register Tick Timer 2 CounterTick timer 2 Counter Board Control Register Watchdog Timer Control Register Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control Register Programming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter Summary Dmac Local Bus Interrupter Status Register bits SIG1 LM0LM1 SIG0 SW3 SW0SW1 SW2 VME4 VME1VME2 VME3 Local Bus Interrupter Enable Register bits ESIG1 ELM0ELM1 ESIG0 ESW3 ESW0ESW1 ESW2 EIRQ4 EIRQ1EIRQ2 EIRQ3 Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits Sysf Level WPE Level Interrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ6 VIRQ5 Level VBR Vector Base Register Control Register Connects to pin 16 of the Remote Status and Control Connects to pin 17 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Enint Miscellaneous Control Register 100 Computer Group Literature Center Web Site Gcsr Programming Model 102 Computer Group Literature Center Web Site Gcsr Programming Model Programming the Gcsr Shows a summary of the Gcsr VMEchip2 Memory Map Gcsr SummaryLocal Bus VMEchip2 Revision Register VMEchip2 ID RegisterVMEchip2 LM/SIG Register LM2 RST LM3VMEchip2 Board Status/Control Register ISF General Purpose Register Local Bus $FFF40110/VMEbus $XXY8 16 bits Local Bus $FFF40118/VMEbus $XXYC 16 bits MC2 Chip Flash and Prom Interface MC2 Chip Initialization Bbram Interface 82596CA LAN InterfaceMPU Port and MPU Channel Attention MC68060-Bus Master Support for 82596CA Lanc Bus Error Lanc Interrupt 53C710 Scsi Controller InterfaceSram Memory Controller NON-ECC Dram Memory Controller Z85230 SCC Interface Dram PerformanceClock Budget Operating Conditions Address Range SCC Device Number Tick Timers Watchdog Timer Local Bus TimerMemory Map of the MC2 Chip Registers Memory Map of the MC2 Chip Registers Programming Model MC2 Chip Revision Register MC2 Chip ID Register General Control Register SCCIT10 Number of Z85230s Interrupt Vector Base Register Interrupt Source IV3-IV0 Daisy Chain Priority Interrupt Vector Base Register Encoding Priority Tick Timer 1 and 2 Compare and Counter Registers Programming the Tick Timers Tick Timer 1 Compare Register Tick Timer 1 CounterTick Timer 2 Compare Register LSB Prescaler Count Register Tick Timer 2 Counter Tick Timer 1 and 2 Control Registers Prescaler Clock Adjust Register Tick Timer 2 Control Register Tick Timer 1 Control RegisterOVF3-OVF0 Tick Timer 2 Interrupt Control Register Tick Timer Interrupt Control RegistersTick Timer 4 Interrupt Control Register Tick Timer 3 Interrupt Control Register Tick Timer 1 Interrupt Control Register IEN Dram Parity Error Interrupt Control RegisterIL2-IL0 Iclr SCC Interrupt Control Register Tick Timer 3 and 4 Control Registers Tick Timer 4 Control RegisterTick Timer 3 Control Register Dram Space Base Address Register Dram and Sram Memory Controller Registers Dram Space Size Register Sram Space Base Address Register Dram Size Control Bit Encoding DRAM/SRAM Options RegisterDZ2 DZ0 Memory Size 28F020 256K x 8 Flash memory devices are used Sram Size Control Bit EncodingF0 set to a 0 indicates that one 28F016SA 2M x 8 Flash Memory device is used. F0 set to a 1 indicates that four SZ1 SZ0 Memory Size Sram Space Size Register LTO, EXT, Prty Lanc Error Status Register Plty 82596CA Lanc Interrupt Control Register Lanc Bus Error Interrupt Control Register General Purpose Inputs Register Scsi Error Status Register V11 MVME172 Version Register Scsi Interrupt Control Register Tick Timer 3 and 4 Compare and Counter Registers Tick Timer 3 Compare RegisterTick Timer 3 Counter Tick Timer 4 Compare Register Tick Timer 4 CounterBus Clock Register Prom Access Time Control Register ET2 Prom Access = NAt 25 MHz where N = At 33 MHz where N = FT2 Flash Access = N Flash Access Time Control Register Abort Switch Interrupt Control Register Reset Switch Control Register Watchdog Timer Control Register Access and Watchdog Time Base Select Register Wdto These bits define the watchdog time-out periodBit Time-out Encoding Dram Control Register Alternate MPU Status RegisterPAREN-PARINT Clock tick Programming Model Bit Prescaler Count Register IP2 Chip General Description Local Bus to IndustryPack DMA Controllers IP2 Chip Clocking Environments and Performance IP2 Chip Clock Cycles Error Reporting as a Local Bus Master Error ReportingFollowing paragraphs describe the IP2 chip error reporting Error Reporting as a Local Bus Slave IndustryPack Error Reporting Overall Memory Map This status bit is cleared by writing a one to it This bit is readable and writable Register Register Name Register Bit Names Offset IP2 Chip Memory Map Control and Status Registers DMA Rotat Dint Dien Diclr Chani TBL $5B DMAc LB Dmac for Chip Revision Register Chip ID Register Vector Base Register IV2-0 Interrupt Source IPa, IPb, IPc, IPd Memory Base Address Registers IPb Memory Base Address Registers IPa or Double Size IPab Memory Base Address Registers IPd Memory Base Address Registers IPa, IPb, IPc, IPd Memory Size RegistersIPc or Double Size IPcd Memory Base Address Registers Not used on 200/300-Series MVME172 BIT NAME$0C When this bit is high, an interrupt is being generated for Corresponding INT status bit. In level-sensitive modeWhen IEN is set, the interrupt is enabled. When IEN is Cleared, the interrupt is disabled MEN IPa, IPb, IPc, and IPd General Control Registers BTD Memory Space Data Width DERR AERRBERR CERR IP32 Setting IP32 to a one enables the IndustryPack bus toSetting it to a zero will enable 8 MHz operation. In this IP Clock Register Where each Dmac has equal access to the MC68060 DMA Arbitration Control RegisterLocal bus. If Rotat is set to a one, the priority is fixed RES IP Reset Register Programming the DMA Controllers Control Word Byte Count DMA Control and Status Register Set Definition DMA Enable Function Ipto DMA Status Register Dint IpendDIL2-DIL0 Dien DEN DMA Control Register Adma Ento Toip DMA Local Bus Address Counter Dmaei DMA Byte Counter DMA IndustryPack Address Counter DMA Table Address Counter IRE Programming the Programmable ClockProgrammable Clock Interrupt Control Register IL2-0 Programmable Clock General Control Register PS2-0CLR PLS Programmable Clock Timer Register Local Bus to IndustryPack Addressing Bit Memory SpaceComments Local Bus to IndustryPack Addressing $00FFFFFB $7FFFFD IPA6-0 Comments IPa I/O Space IPab I/O Space IPA5-0 Comments IPa ID Space Memory Space Accesses IP to Local Bus Data RoutingThis section shows data routing from an IP to the local bus IP to Local Bus Data Routing Space Lbsize LBA IPA ID Space Accesses Mcecc Features Performance Descriptions Specifications Mcecc Specifications Cycle Types ECC Error Reporting Single Bit Error Cycle Type = Burst Read or Non-Burst ReadDouble Bit Error Cycle Type = Burst Read or Non-Burst Read Single Bit Error Cycle Type = Scrub Single Bit Error Cycle Type = Non-Burst WriteDouble Bit Error Cycle Type = Non-Burst Write Triple or Greater Bit Error Cycle Type = Non-Burst Write Scrub Error LoggingDouble Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Scrub Chip Defaults RefreshArbitration Programming Model Offset Name Mcecc Internal Register Memory Map, PartMcecc Base Address = $FFF43000 1st $FFF43100 2nd Register Base BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address D31 D30 D29 D28 D27 D26 D25 D24 Register Bit Names Scrub SAC7 SAC6 SAC5 SAC4 Addr Cntr 1st $FFF43000/2nd $FFF43100 8-bits MSIZ2-MSIZ0 Memory Configuration Register Dummy Register RB3 Read Bit 3 is a read only bit that is alwaysRB4 Read Bit 4 is a read only bit that is always Base Address Register Difference from MEMC040 noneBit assignments for the Base Address Register are RWB3 Read/Write Bit 3 is a general purpose read/write bit Bit assignments for the Dram Control Register are RWB5 Read/Write Bit 5 is a general purpose read/write bit Bclk Frequency Register Data Control Register Mcecc Scrub Control Register This register contains bits 7-0 of the Scrub Period Register Scrub Period Register Bits Chip Prescaler Counter Scrub Time On/Time Off RegisterSTOFF2-STOFF0 STON2-STON0 Scrubber Time OffScrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF4304C/2nd $FFF4314C 8-bits Error Logger Register Error Address Bits 1st $FFF43064/2nd $FFF43164 8-bits Error Syndrome Register Defaults RegisterRSIZ2-RSIZ0 SELI1, SELI0 Dram Array SizeRegister Base Address Nocache RESST2-RESST0 Initialization Mcecc Syndrome Decode Bank in Error Bit in Error Syndrome Code Bank C Bank a Mcecc Document Title Motorola Publication Number Motorola Computer Group Documents Literature Updates Manufacturers’ DocumentsTable A-2. Manufacturers’ Documents Table A-2. Manufacturers’ Documents Related Documentation VMEchip2 Tick Timer 1 Periodic Interrupt Example BUsing Interrupts on the MVME172 Refer to the Vector Base Register Step Register and Address Action and Reference Using Interrupts on the MVME172 Page Index IN-2 DMA Gcsr Lanc IN-6 MPU SCC Scsi Mcecc IN-10 IN-11 Index MVME172 MVME172 Programmer’s Reference Guide