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Motorola MVME172 manual Control Word Byte Count

Models: MVME172

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IP2 Chip

Each DMAC’s control is divided into two registers. The first register is only accessible by the processor. The second register can be loaded by the processor in the direct mode and by the DMAC in the command chaining mode.

There is a case when the byte count for a DMA (to local bus) operation is initially set larger than the actual received data. In this case, there is residual data in the internal data paths of the DMA controller. To flush the data, set the byte count register to 0. A normal termination of the DMA occurs after the byte count register has been initialized to zero. Do not use the DMAEND signal on the IP bus to terminate a DMA operation for this case. This would terminate the DMA process in such a way that the data could not be flushed from the fifo data path.

Once a DMAC is enabled, its counter and control registers should not be modified by software. When the command chaining mode is used, the list of commands must be in local (not IP), 32-bit memory and the entries must be aligned to a 16-byte boundary. That is, the address which is loaded into the DMA table address counter must have bits three through zero set to a zero. This is true for the initial value which is loaded by the processor or the subsequent values which are loaded by the command chaining logic. If they are not set to zero, the command chaining process will halt.

A DMAC command packet includes a control word that defines: single command interrupt enable, DMA transfer direction, IndustryPack data width, sDMA or aDMA selection, and the DMAEND direction and usage. The format of the control word is the same as control register 2. The command packet also includes a local bus address, an IP address, a byte count, and a pointer to the next command packet in the list. The end of a command is indicated by setting bit 0 or 1 of the next command address. The command packet format is shown in the following table.

Entry					Function

0	31			Address of Next Command Packet		0
0				Address of Next Command Packet

1	31				Local Bus Address	0
1					Local Bus Address

2	31	Control Word	24	23	Byte Count	0
2		Control Word			Byte Count

3	31		24	23	IndustryPack Address DMA	0
3					IndustryPack Address DMA

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Motorola MVME172 manual Control Word Byte Count

Contents

MVME172 VME Embedded Controller Programmer’s Reference GuideRestricted Rights Legend Preface Recent Updates Page Page Contents VMEchip2 Page Page MC2 Chip Xii IP2 Chip Chapter Mcecc Index Figures Xvii Xviii Introduction OverviewBoard Description and Memory Maps MVME172 Features Summary Feature 200/300-Series Fuses LAN power SCON, LAN, Fuse LAN powerRequirements Functional Description Block DiagramsNo-VMEbus-Interface Option 300-Series MVME172 Block Diagram Block Diagram 500-Series MVME172Redundant Functions in the VMEchip2 and MC2 Chip VMEchip2 MC2 Chip Address Bit #Memory Maps VMEbus Interface and VMEchip2Local Bus Memory Map Normal Address Range300-Series MVME172 Local Bus Memory Map Memory Maps 500-Series MVME172 Local Bus Memory Map Cache Accessed Width InhibitDevices Port Software Address Range Memory Maps Address Range Devices Accessed Port Size Width 300-Series MVME172 Local I/O Devices Memory Map$FFFBC000 $FFFBC01F $FFFBC800 $FFFBC81F Memory Maps 500-Series MVME172 Local I/O Devices Memory Map Address Range Device Port Size Width2KB $FFFBC800 $FFFBC81F Board Description and Memory Maps Detailed I/O Memory Maps Tables 1-7 through 1-17 give the detailed memory maps forVMEchip2 Memory Map Sheet 1 OffsetThis sheet begins on facing VMEchip2 Memory Map Sheet 2 PRECompare Register Counter Overflow VMEchip2 Memory Map Sheet 3 Offsets Bit NumbersMC2 Chip Base Address = $FFF42000 MC2 Chip Register MapOffset D31-D24 D23-D16 D15-D8 D7-D0 IP2 Chip Overall Memory Map Address Range Selected Device Port Width Size10. IP2 Chip Memory Map Control and Status Registers IP2 Chip Base Address = $FFFBC000DMA Dlbe Chani TBL $51 DMAc INT Dlbe Ipend Chani TBL Ipto Done 11. Mcecc Internal Register Memory Map Mcecc Base Address = $FFF43000 1st $FFF43100 2ndName D31 D30 D29 D28 D27 D26 D25 D24 12. Z85230 SCC Register Addresses Z85230 SCC Register Address13 CA Ethernet LAN Memory Map 14 C710 Scsi Memory Map 15. MK48T58 BBRAM/TOD Clock Memory Map BBRAM/TOD Clock Memory MapAddress Range Description Size Bytes 16. Bbram Configuration Area Memory Map Local Scsi IDFT = Frequency Test x = Must be set to 17. TOD Clock Memory MapAddress Data Bits Function Ecc1memserial 12 characters are followed by four blanks 3992B03A VMEbus Memory Map Interrupt Acknowledge MapVMEbus Accesses to the Local Bus Software Support ConsiderationsInterrupts VMEbus Short I/O Memory MapSources of Local Berr Cache CoherencyLocal Bus Time-out VMEbus Access Time-out Local Dram Parity ErrorBus Error Processing VMEbus BerrDescription of Error Conditions on the MVME172 MPU Parity ErrorMPU TEA Cause Unidentified MPU Off-board ErrorMPU Local Bus Time-out Dmac VMEbus Error Dmac Parity ErrorDmac Off-board Error Dmac LTO ErrorLAN Parity Error Dmac TEA Cause UnidentifiedLAN Off-Board Error LAN LTO ErrorScsi Off-Board Error Scsi Parity ErrorScsi LTO Error Example of the Proper Use of Bus Timers MVME172 MC68060 Indivisible Cycles Illegal Access to IP Modules from External VMEbus Masters Page Summary of Major Features VMEchip2VMEchip2 Introduction Functional Blocks Local Bus to VMEbus InterfaceVMEchip2 Block Diagram VMEchip2 Local Bus to VMEbus Requester VMEchip2 VMEbus to Local Bus Interface Functional BlocksLocal Bus to VMEbus DMA Controller Functional Blocks No Address Increment DMA Transfers Dmac VMEbus Requester Tick and Watchdog Timers PrescalerTick Timers Watchdog TimerVMEbus Interrupter Bus Timer VMEbus System ControllerArbiter Iack Daisy-Chain DriverReset Driver Local Bus Interrupter and Interrupt HandlerFunctional Blocks Lcsr Programming Model Global Control and Status RegistersSummary of the Lcsr is shown in Table VMEchip2 Memory Map Lcsr Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map Lcsr Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Ending Address Register VMEbus Slave Starting Address RegisterVMEbus Slave Address Translation Address Offset Register VMEbus Slave Address Translation Select Register Segment Address Translation Size Select Value$FFF4000C 16 bits WP2 VMEbus Slave Write Post and Snoop Control RegisterSNP2 VMEbus Slave Address Modifier Select Register DATPGM BLKUSR A32SUP SNP1 WP1ADDER1 When this bit is high, the first map decoder responds to Block access cyclesA24 access cycles CyclesA32 access cycles VMEbus supervisory access cycles. When this bit is lowProgramming the Local Bus to VMEbus Map Decoders Bit is low, the first map decoder does not respond toVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register D16Segment defined by map decoder 3. When this bit is Decoder 3. Because the local bus to VMEbus interfaceSegment defined by map decoder 2. When this bit is Bus map decoderDecoder 2. Since the local bus to VMEbus interface does Not support block transfers, the block transfer addressSegment defined by map decoder 1. When this bit is Decoder 1. Because the local bus to VMEbus interfaceVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register Local Bus to VMEbus Enable Control Register EN1EN2 EN3Local Bus to VMEbus I/O Control Register I2WP I2ENProgramming the VMEchip2 DMA Controller Dmac Registers Dmac Command Table FormatEntry Function Prom Decoder, Sram and DMA Control Register SramsTblsc ROM0Local Bus to VMEbus Requester Control Register LvreqlLvrwd LvfairDHB RobnDfair DtblDEN DhaltTvme LincVinc SNPVME AM Dmac VMEbus Address Counter Dmac Local Bus Address CounterDmac VMEbus Address Counter VMEbus Interrupter Control Register Table Address CounterDmac Byte Counter Irql IrqsIrqc IRQ1SVMEbus Interrupter Vector Register MPU Status and DMA Interrupt Count RegisterDmac Status Register DoneVME TBLProgramming the Tick and Watchdog Timers VMEbus Arbiter Time-out Control RegisterVgto Time onLbto VatoPrescaler Control Register Prescaler register = 256 B clock MHzTick Timer 1 Counter Tick Timer 1 Compare RegisterTick timer 1 Compare Register Tick Timer 2 Counter Tick Timer 2 Compare RegisterTick timer 2 Counter Board Control Register Watchdog Timer Control Register Tick Timer 2 Control Register Tick Timer 1 Control Register Prescaler CounterProgramming the Local Bus Interrupter Local Bus Interrupter Summary Interrupt Vector Priority for Simultaneous InterruptsDmac Local Bus Interrupter Status Register bits LM0 LM1SIG0 SIG1SW0 SW1SW2 SW3VME1 VME2VME3 VME4Local Bus Interrupter Enable Register bits ELM0 ELM1ESIG0 ESIG1ESW0 ESW1ESW2 ESW3EIRQ1 EIRQ2EIRQ3 EIRQ4Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits Sysf Level WPE Level Interrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ6 VIRQ5 Level Vector Base Register VBRControl Register Connects to pin 17 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Miscellaneous Control Register Enint100 Computer Group Literature Center Web Site Gcsr Programming Model 102 Computer Group Literature Center Web Site Programming the Gcsr Gcsr Programming ModelVMEchip2 Memory Map Gcsr Summary Shows a summary of the GcsrLocal Bus VMEchip2 ID Register VMEchip2 Revision RegisterVMEchip2 LM/SIG Register LM2 LM3 VMEchip2 Board Status/Control RegisterISF RSTGeneral Purpose Register Local Bus $FFF40110/VMEbus $XXY8 16 bits Local Bus $FFF40118/VMEbus $XXYC 16 bits MC2 Chip MC2 Chip Initialization Flash and Prom Interface82596CA LAN Interface Bbram InterfaceMPU Port and MPU Channel Attention Lanc Bus Error MC68060-Bus Master Support for 82596CA53C710 Scsi Controller Interface Sram Memory ControllerNON-ECC Dram Memory Controller Lanc InterruptDram Performance Z85230 SCC InterfaceClock Budget Operating Conditions Tick Timers Address Range SCC Device NumberLocal Bus Timer Watchdog TimerMemory Map of the MC2 Chip Registers Memory Map of the MC2 Chip Registers Programming Model MC2 Chip ID Register MC2 Chip Revision RegisterGeneral Control Register Interrupt Vector Base Register SCCIT10 Number of Z85230sInterrupt Vector Base Register Encoding Priority Interrupt Source IV3-IV0 Daisy Chain PriorityProgramming the Tick Timers Tick Timer 1 and 2 Compare and Counter RegistersTick Timer 1 Counter Tick Timer 1 Compare RegisterTick Timer 2 Compare Register Tick Timer 2 Counter LSB Prescaler Count RegisterPrescaler Clock Adjust Register Tick Timer 1 and 2 Control RegistersTick Timer 1 Control Register Tick Timer 2 Control RegisterOVF3-OVF0 Tick Timer Interrupt Control Registers Tick Timer 4 Interrupt Control RegisterTick Timer 3 Interrupt Control Register Tick Timer 2 Interrupt Control RegisterTick Timer 1 Interrupt Control Register Dram Parity Error Interrupt Control Register IL2-IL0Iclr IENSCC Interrupt Control Register Tick Timer 4 Control Register Tick Timer 3 and 4 Control RegistersTick Timer 3 Control Register Dram and Sram Memory Controller Registers Dram Space Base Address RegisterSram Space Base Address Register Dram Space Size RegisterDRAM/SRAM Options Register Dram Size Control Bit EncodingDZ2 DZ0 Memory Size Sram Size Control Bit Encoding F0 set to a 0 indicates that one 28F016SA 2M x 8 FlashMemory device is used. F0 set to a 1 indicates that four 28F020 256K x 8 Flash memory devices are usedSram Space Size Register SZ1 SZ0 Memory SizeLanc Error Status Register LTO, EXT, Prty82596CA Lanc Interrupt Control Register PltyLanc Bus Error Interrupt Control Register Scsi Error Status Register General Purpose Inputs RegisterV11 MVME172 Version Register Scsi Interrupt Control Register Tick Timer 3 Compare Register Tick Timer 3 and 4 Compare and Counter RegistersTick Timer 3 Counter Tick Timer 4 Counter Tick Timer 4 Compare RegisterBus Clock Register ET2 Prom Access = N Prom Access Time Control RegisterAt 25 MHz where N = At 33 MHz where N = Flash Access Time Control Register FT2 Flash Access = NAbort Switch Interrupt Control Register Reset Switch Control Register Watchdog Timer Control Register Wdto These bits define the watchdog time-out period Access and Watchdog Time Base Select RegisterBit Time-out Encoding Dram Control Register MPU Status Register PAREN-PARINTClock tick AlternateProgramming Model Bit Prescaler Count Register IP2 Chip General Description Local Bus to IndustryPack DMA Controllers IP2 Chip Clocking Environments and Performance IP2 Chip Clock Cycles Error Reporting Following paragraphs describe the IP2 chip error reportingError Reporting as a Local Bus Slave Error Reporting as a Local Bus MasterIndustryPack Error Reporting Overall Memory Map This bit is readable and writable This status bit is cleared by writing a one to itIP2 Chip Memory Map Control and Status Registers Register Register Name Register Bit Names OffsetDMA Rotat Dint Dien Diclr Chani TBL $5B DMAc LB Dmac for Chip ID Register Chip Revision RegisterVector Base Register IPa, IPb, IPc, IPd Memory Base Address Registers IV2-0 Interrupt SourceIPa or Double Size IPab Memory Base Address Registers IPb Memory Base Address RegistersIPa, IPb, IPc, IPd Memory Size Registers IPc or Double Size IPcd Memory Base Address RegistersNot used on 200/300-Series MVME172 IPd Memory Base Address RegistersBIT NAME$0C Corresponding INT status bit. In level-sensitive mode When IEN is set, the interrupt is enabled. When IEN isCleared, the interrupt is disabled When this bit is high, an interrupt is being generated forIPa, IPb, IPc, and IPd General Control Registers MENBTD Memory Space Data Width AERR BERRCERR DERRSetting IP32 to a one enables the IndustryPack bus to Setting it to a zero will enable 8 MHz operation. In thisIP Clock Register IP32DMA Arbitration Control Register Where each Dmac has equal access to the MC68060Local bus. If Rotat is set to a one, the priority is fixed IP Reset Register RESProgramming the DMA Controllers Control Word Byte Count DMA Enable Function DMA Control and Status Register Set DefinitionDMA Status Register IptoIpend DIL2-DIL0Dien DintDEN DMA Control Register Adma Toip EntoDmaei DMA Local Bus Address CounterDMA IndustryPack Address Counter DMA Byte CounterDMA Table Address Counter Programming the Programmable Clock Programmable Clock Interrupt Control RegisterIL2-0 IREPS2-0 Programmable Clock General Control RegisterCLR Programmable Clock Timer Register PLSBit Memory Space Local Bus to IndustryPack AddressingComments Local Bus to IndustryPack Addressing $00FFFFFB $7FFFFD IPa I/O Space IPA6-0 CommentsIPab I/O Space IPa ID Space IPA5-0 CommentsIP to Local Bus Data Routing Memory Space AccessesThis section shows data routing from an IP to the local bus IP to Local Bus Data Routing ID Space Accesses Space Lbsize LBA IPAFeatures MceccPerformance Mcecc Specifications Descriptions SpecificationsECC Cycle TypesSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Error ReportingDouble Bit Error Cycle Type = Burst Read or Non-Burst Read Single Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Non-Burst WriteTriple or Greater Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = ScrubError Logging Double Bit Error Cycle Type = ScrubTriple or Greater Bit Error Cycle Type = Scrub ScrubRefresh Chip DefaultsArbitration Programming Model Mcecc Internal Register Memory Map, Part Mcecc Base Address = $FFF43000 1st $FFF43100 2ndRegister Offset NameBase BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address Register Bit Names D31 D30 D29 D28 D27 D26 D25 D24Scrub SAC7 SAC6 SAC5 SAC4 Addr Cntr 1st $FFF43000/2nd $FFF43100 8-bits Memory Configuration Register MSIZ2-MSIZ0RB3 Read Bit 3 is a read only bit that is always Dummy RegisterRB4 Read Bit 4 is a read only bit that is always Difference from MEMC040 none Base Address RegisterBit assignments for the Base Address Register are Bit assignments for the Dram Control Register are RWB3 Read/Write Bit 3 is a general purpose read/write bitRWB5 Read/Write Bit 5 is a general purpose read/write bit Bclk Frequency Register Data Control Register Mcecc Scrub Control Register Scrub Period Register Bits This register contains bits 7-0 of the Scrub Period RegisterScrub Time On/Time Off Register Chip Prescaler CounterSTOFF2-STOFF0 Scrubber Time Off STON2-STON0Scrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF4304C/2nd $FFF4314C 8-bits Error Logger Register Error Address Bits 1st $FFF43064/2nd $FFF43164 8-bits Defaults Register Error Syndrome RegisterRSIZ2-RSIZ0 Dram Array Size SELI1, SELI0Register Base Address RESST2-RESST0 NocacheInitialization Mcecc Bank in Error Bit in Error Syndrome Code Syndrome DecodeBank C Bank a Mcecc Motorola Computer Group Documents Document Title Motorola Publication NumberManufacturers’ Documents Literature UpdatesTable A-2. Manufacturers’ Documents Table A-2. Manufacturers’ Documents Related Documentation BUsing Interrupts on the MVME172 VMEchip2 Tick Timer 1 Periodic Interrupt ExampleStep Register and Address Action and Reference Refer to the Vector Base RegisterUsing Interrupts on the MVME172 Page Index IN-2 DMA Gcsr Lanc IN-6 MPU SCC Scsi Mcecc IN-10 IN-11 Index MVME172 Programmer’s Reference Guide MVME172