LCSR Programming Model

Local Bus Interrupter Enable Register (bits 0-7)

ADR/SIZ

 

 

$FFF4006C (8 bits of 32)

 

 

 

 

 

 

 

 

 

 

 

BIT

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

NAME

SPARE

EIRQ7

EIRQ6

EIRQ5

EIRIQ4

EIRQ3

EIRQ2

EIRQ1

 

 

 

 

 

 

 

 

 

OPER

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

RESET

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

0 PSL

 

 

 

 

 

 

 

 

 

This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled. The enable bit does not clear edge-sensitive interrupts or prevent the flip flop from being set. If necessary, edge-sensitive interrupters should be cleared to remove any old interrupts and then enabled.

EIRQ1

Enable VMEbus IRQ1 interrupt.

EIRQ2

Enable VMEbus IRQ2 interrupt.

EIRQ3

Enable VMEbus IRQ3 interrupt.

EIRQ4

Enable VMEbus IRQ4 interrupt.

EIRQ5

Enable VMEbus IRQ5 interrupt.

EIRQ6

Enable VMEbus IRQ6 interrupt.

EIRQ7

Enable VMEbus IRQ7 interrupt.

SPARE

SPARE.

2

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Image 163
Motorola MVME172 manual EIRQ1, EIRQ2, EIRQ3, EIRQ4, EIRQ5, EIRQ6, EIRQ7