Motorola MVME172 manual Dfair, Dtbl, Den, Dhalt, Dmac Control Register 2 bits

		LCSR Programming Model
	3	VMEbus.
		Release when a BRx* signal is active on the
		VMEbus or the time on timer has expired.
DFAIR	When this bit is high, the DMAC requester operates in the
	fair mode. It waits until its request level is inactive before
	requesting the VMEbus. When this bit is low, the DMAC
	requester does not operate in the fair mode.
DTBL	The DMAC operates in the direct mode when this bit is
	low, and it operates in the command chaining mode when
	this bit is high.
DEN	The DMAC is enabled when this bit is set high. This bit
	always reads 0.
DHALT	When this bit is high, the DMAC halts at the end of a
	command when the DMAC is operating in the command
	chaining mode. When this bit is low, the DMAC executes
	the next command in the list.

DMAC Control Register 2 (bits 8-15)

ADR/SIZ				$FFF40034 (8 bits [7 USED] of 32)
BIT	15	14		13	12	11	10	9	8
NAME	INTE		SNP			VINC	LINC	TVME	D16
OPER	R/W		R/W			R/W	R/W	R/W	R/W
RESET	0 PS		0 PS			0 PS	0 PS	0 PS	0 PS

This portion of the control register is loaded by the processor or by the DMAC when it loads the command word from the command packet. Because this register is loaded from the command packet in the command chaining mode, the descriptions here also apply to the control word in the command packet.

D16	When this bit is high, the DMAC executes D16 cycles on
	the VMEbus. When this bit is low, the DMAC executes
	D32/D64 cycles on the VMEbus.

2

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