Manuals / Motorola / Computer Equipment / Network Card

Motorola MVME172 manual IP2 Chip

Models: MVME172

1 354

Download 354 pages 60.32 Kb

Page 240

4

IP2 Chip

addresses are not aligned, so the local bus and the IndustryPack can operate at their maximum data transfer sizes. The FIFO also buffers enough data so that accesses to the local bus are in the burst mode.

Each DMAC also supports command chaining through the use of a singly- linked list built in local (not IP) memory. Each entry in the list includes an IP address, a local bus address, a byte count, a control word, and a pointer to the next entry. When the command chaining mode is enabled, the DMAC reads and executes commands from the list in local memory until all commands are executed.

Each DMAC can be programmed to generate an interrupt request when any specific table entry has completed, when the byte count reaches zero, when an error condition occurs, or when the DMAEND* signal is asserted by the IndustryPack.

The DMA arbiter has two modes of operation. One mode is to implement a round robin type of arbitration, which guarantees equal access to the local bus. The other method is to set the arbitration priority to one of four states. In this case, the priority is constant with one DMA channel having the highest priority, and the other three having the second, third, and fourth highest priority.

Note that the IP specification supports a DMA burst where the DMA cycles can be executed back to back. The DMA arbiter logic will not release a DMA channel until a burst of IP cycles are completed, if the burst protocol is observed. However, if the burst protocol is not observed, the arbiter is released and the next DMA request/grant is resolved. This takes two clock cycles due to the asynchronous clocks controlling the MC68060 local bus and the IP busses. The IP designer should take this into consideration if maximum DMA bandwidth availability is required.

Note also that when the DMA register context is updated for the next command packet, a DMA function is used. The state of the snoop control signals for this DMA function is determined by the settings of jumper J26 (as is the state of the snoop control signals for all other DMA cycle types). Refer to the Hardware Preparation section of your MVME172 installation and use manual.

4-4	Computer Group Literature Center Web Site

Image 240

Motorola MVME172 manual IP2 Chip

Contents

MVME172 VME Embedded Controller Programmer’s Reference GuideRestricted Rights Legend Preface Recent Updates Page Page Contents VMEchip2 Page Page MC2 Chip Xii IP2 Chip Chapter Mcecc Index Figures Xvii Xviii Introduction OverviewBoard Description and Memory Maps MVME172 Features Summary Fuses LAN power SCON, LAN, Fuse LAN power Feature 200/300-SeriesRequirements Block Diagrams Functional DescriptionNo-VMEbus-Interface Option 300-Series MVME172 Block Diagram Block Diagram 500-Series MVME172Redundant Functions in the VMEchip2 and MC2 Chip VMEchip2 MC2 Chip Address Bit #Memory Maps VMEbus Interface and VMEchip2Local Bus Memory Map Normal Address Range300-Series MVME172 Local Bus Memory Map Memory Maps Cache Accessed Width Inhibit 500-Series MVME172 Local Bus Memory MapDevices Port Software Address Range Memory Maps Address Range Devices Accessed Port Size Width 300-Series MVME172 Local I/O Devices Memory Map$FFFBC000 $FFFBC01F $FFFBC800 $FFFBC81F Memory Maps 500-Series MVME172 Local I/O Devices Memory Map Address Range Device Port Size Width2KB $FFFBC800 $FFFBC81F Board Description and Memory Maps Detailed I/O Memory Maps Tables 1-7 through 1-17 give the detailed memory maps forVMEchip2 Memory Map Sheet 1 OffsetThis sheet begins on facing VMEchip2 Memory Map Sheet 2 PRECompare Register Counter Overflow VMEchip2 Memory Map Sheet 3 Offsets Bit NumbersMC2 Chip Register Map MC2 Chip Base Address = $FFF42000Offset D31-D24 D23-D16 D15-D8 D7-D0 IP2 Chip Overall Memory Map Address Range Selected Device Port Width Size10. IP2 Chip Memory Map Control and Status Registers IP2 Chip Base Address = $FFFBC000DMA Dlbe Chani TBL $51 DMAc INT Dlbe Ipend Chani TBL Ipto Done 11. Mcecc Internal Register Memory Map Mcecc Base Address = $FFF43000 1st $FFF43100 2ndName D31 D30 D29 D28 D27 D26 D25 D24 12. Z85230 SCC Register Addresses Z85230 SCC Register Address13 CA Ethernet LAN Memory Map 14 C710 Scsi Memory Map BBRAM/TOD Clock Memory Map 15. MK48T58 BBRAM/TOD Clock Memory MapAddress Range Description Size Bytes 16. Bbram Configuration Area Memory Map Local Scsi ID17. TOD Clock Memory Map FT = Frequency Test x = Must be set toAddress Data Bits Function Ecc1memserial 12 characters are followed by four blanks 3992B03A VMEbus Memory Map Interrupt Acknowledge MapVMEbus Accesses to the Local Bus Software Support ConsiderationsInterrupts VMEbus Short I/O Memory MapCache Coherency Sources of Local BerrLocal Bus Time-out VMEbus Access Time-out Local Dram Parity ErrorBus Error Processing VMEbus BerrDescription of Error Conditions on the MVME172 MPU Parity ErrorMPU Off-board Error MPU TEA Cause UnidentifiedMPU Local Bus Time-out Dmac VMEbus Error Dmac Parity ErrorDmac Off-board Error Dmac LTO ErrorLAN Parity Error Dmac TEA Cause UnidentifiedLAN Off-Board Error LAN LTO ErrorScsi Parity Error Scsi Off-Board ErrorScsi LTO Error Example of the Proper Use of Bus Timers MVME172 MC68060 Indivisible Cycles Illegal Access to IP Modules from External VMEbus Masters Page Summary of Major Features VMEchip2VMEchip2 Introduction Functional Blocks Local Bus to VMEbus InterfaceVMEchip2 Block Diagram VMEchip2 Local Bus to VMEbus Requester VMEchip2 VMEbus to Local Bus Interface Functional BlocksLocal Bus to VMEbus DMA Controller Functional Blocks No Address Increment DMA Transfers Dmac VMEbus Requester Tick and Watchdog Timers PrescalerTick Timers Watchdog TimerVMEbus Interrupter Bus Timer VMEbus System ControllerArbiter Iack Daisy-Chain DriverReset Driver Local Bus Interrupter and Interrupt HandlerFunctional Blocks Lcsr Programming Model Global Control and Status RegistersSummary of the Lcsr is shown in Table VMEchip2 Memory Map Lcsr Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map Lcsr Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Ending Address Register VMEbus Slave Starting Address RegisterVMEbus Slave Address Translation Address Offset Register VMEbus Slave Address Translation Select Register Segment Address Translation Size Select Value$FFF4000C 16 bits VMEbus Slave Write Post and Snoop Control Register WP2SNP2 VMEbus Slave Address Modifier Select Register DATPGM BLKA32 USRSUP WP1 SNP1ADDER1 When this bit is high, the first map decoder responds to Block access cyclesA24 access cycles CyclesA32 access cycles VMEbus supervisory access cycles. When this bit is lowProgramming the Local Bus to VMEbus Map Decoders Bit is low, the first map decoder does not respond toVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register D16Segment defined by map decoder 3. When this bit is Decoder 3. Because the local bus to VMEbus interfaceSegment defined by map decoder 2. When this bit is Bus map decoderDecoder 2. Since the local bus to VMEbus interface does Not support block transfers, the block transfer addressSegment defined by map decoder 1. When this bit is Decoder 1. Because the local bus to VMEbus interfaceVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register Local Bus to VMEbus Enable Control Register EN1EN2 EN3Local Bus to VMEbus I/O Control Register I2WP I2ENProgramming the VMEchip2 DMA Controller Dmac Command Table Format Dmac RegistersEntry Function Prom Decoder, Sram and DMA Control Register SramsTblsc ROM0Local Bus to VMEbus Requester Control Register LvreqlLvrwd LvfairDHB RobnDfair DtblDEN DhaltTvme LincVinc SNPVME AM Dmac Local Bus Address Counter Dmac VMEbus Address CounterDmac VMEbus Address Counter Table Address Counter VMEbus Interrupter Control RegisterDmac Byte Counter Irql IrqsIrqc IRQ1SVMEbus Interrupter Vector Register MPU Status and DMA Interrupt Count RegisterDmac Status Register DoneVME TBLProgramming the Tick and Watchdog Timers VMEbus Arbiter Time-out Control RegisterVgto Time onLbto VatoPrescaler Control Register Prescaler register = 256 B clock MHzTick Timer 1 Compare Register Tick Timer 1 CounterTick timer 1 Compare Register Tick Timer 2 Compare Register Tick Timer 2 CounterTick timer 2 Counter Board Control Register Watchdog Timer Control Register Tick Timer 2 Control Register Tick Timer 1 Control Register Prescaler CounterProgramming the Local Bus Interrupter Local Bus Interrupter Summary Interrupt Vector Priority for Simultaneous InterruptsDmac Local Bus Interrupter Status Register bits LM0 LM1SIG0 SIG1SW0 SW1SW2 SW3VME1 VME2VME3 VME4Local Bus Interrupter Enable Register bits ELM0 ELM1ESIG0 ESIG1ESW0 ESW1ESW2 ESW3EIRQ1 EIRQ2EIRQ3 EIRQ4Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits Sysf Level WPE Level Interrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ6 VIRQ5 Level Vector Base Register VBRControl Register Connects to pin 16 of the Remote Status and Control Connects to pin 17 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Miscellaneous Control Register Enint100 Computer Group Literature Center Web Site Gcsr Programming Model 102 Computer Group Literature Center Web Site Programming the Gcsr Gcsr Programming ModelShows a summary of the Gcsr VMEchip2 Memory Map Gcsr SummaryLocal Bus VMEchip2 Revision Register VMEchip2 ID RegisterVMEchip2 LM/SIG Register LM2 LM3 VMEchip2 Board Status/Control RegisterISF RSTGeneral Purpose Register Local Bus $FFF40110/VMEbus $XXY8 16 bits Local Bus $FFF40118/VMEbus $XXYC 16 bits MC2 Chip MC2 Chip Initialization Flash and Prom InterfaceBbram Interface 82596CA LAN InterfaceMPU Port and MPU Channel Attention Lanc Bus Error MC68060-Bus Master Support for 82596CA53C710 Scsi Controller Interface Sram Memory ControllerNON-ECC Dram Memory Controller Lanc InterruptZ85230 SCC Interface Dram PerformanceClock Budget Operating Conditions Tick Timers Address Range SCC Device NumberWatchdog Timer Local Bus TimerMemory Map of the MC2 Chip Registers Memory Map of the MC2 Chip Registers Programming Model MC2 Chip ID Register MC2 Chip Revision RegisterGeneral Control Register Interrupt Vector Base Register SCCIT10 Number of Z85230sInterrupt Vector Base Register Encoding Priority Interrupt Source IV3-IV0 Daisy Chain PriorityProgramming the Tick Timers Tick Timer 1 and 2 Compare and Counter RegistersTick Timer 1 Compare Register Tick Timer 1 CounterTick Timer 2 Compare Register Tick Timer 2 Counter LSB Prescaler Count RegisterPrescaler Clock Adjust Register Tick Timer 1 and 2 Control RegistersTick Timer 2 Control Register Tick Timer 1 Control RegisterOVF3-OVF0 Tick Timer Interrupt Control Registers Tick Timer 4 Interrupt Control RegisterTick Timer 3 Interrupt Control Register Tick Timer 2 Interrupt Control RegisterTick Timer 1 Interrupt Control Register Dram Parity Error Interrupt Control Register IL2-IL0Iclr IENSCC Interrupt Control Register Tick Timer 3 and 4 Control Registers Tick Timer 4 Control RegisterTick Timer 3 Control Register Dram and Sram Memory Controller Registers Dram Space Base Address RegisterSram Space Base Address Register Dram Space Size RegisterDram Size Control Bit Encoding DRAM/SRAM Options RegisterDZ2 DZ0 Memory Size Sram Size Control Bit Encoding F0 set to a 0 indicates that one 28F016SA 2M x 8 FlashMemory device is used. F0 set to a 1 indicates that four 28F020 256K x 8 Flash memory devices are usedSram Space Size Register SZ1 SZ0 Memory SizeLanc Error Status Register LTO, EXT, Prty82596CA Lanc Interrupt Control Register PltyLanc Bus Error Interrupt Control Register Scsi Error Status Register General Purpose Inputs RegisterV11 MVME172 Version Register Scsi Interrupt Control Register Tick Timer 3 and 4 Compare and Counter Registers Tick Timer 3 Compare RegisterTick Timer 3 Counter Tick Timer 4 Compare Register Tick Timer 4 CounterBus Clock Register Prom Access Time Control Register ET2 Prom Access = NAt 25 MHz where N = At 33 MHz where N = Flash Access Time Control Register FT2 Flash Access = NAbort Switch Interrupt Control Register Reset Switch Control Register Watchdog Timer Control Register Access and Watchdog Time Base Select Register Wdto These bits define the watchdog time-out periodBit Time-out Encoding Dram Control Register MPU Status Register PAREN-PARINTClock tick AlternateProgramming Model Bit Prescaler Count Register IP2 Chip General Description Local Bus to IndustryPack DMA Controllers IP2 Chip Clocking Environments and Performance IP2 Chip Clock Cycles Error Reporting Following paragraphs describe the IP2 chip error reportingError Reporting as a Local Bus Slave Error Reporting as a Local Bus MasterIndustryPack Error Reporting Overall Memory Map This bit is readable and writable This status bit is cleared by writing a one to itIP2 Chip Memory Map Control and Status Registers Register Register Name Register Bit Names OffsetDMA Rotat Dint Dien Diclr Chani TBL $5B DMAc LB Dmac for Chip ID Register Chip Revision RegisterVector Base Register IPa, IPb, IPc, IPd Memory Base Address Registers IV2-0 Interrupt SourceIPa or Double Size IPab Memory Base Address Registers IPb Memory Base Address RegistersIPa, IPb, IPc, IPd Memory Size Registers IPc or Double Size IPcd Memory Base Address RegistersNot used on 200/300-Series MVME172 IPd Memory Base Address RegistersBIT NAME$0C Corresponding INT status bit. In level-sensitive mode When IEN is set, the interrupt is enabled. When IEN isCleared, the interrupt is disabled When this bit is high, an interrupt is being generated forIPa, IPb, IPc, and IPd General Control Registers MENBTD Memory Space Data Width AERR BERRCERR DERRSetting IP32 to a one enables the IndustryPack bus to Setting it to a zero will enable 8 MHz operation. In thisIP Clock Register IP32Where each Dmac has equal access to the MC68060 DMA Arbitration Control RegisterLocal bus. If Rotat is set to a one, the priority is fixed IP Reset Register RESProgramming the DMA Controllers Control Word Byte Count DMA Enable Function DMA Control and Status Register Set DefinitionDMA Status Register IptoIpend DIL2-DIL0Dien DintDEN DMA Control Register Adma Toip EntoDmaei DMA Local Bus Address CounterDMA IndustryPack Address Counter DMA Byte CounterDMA Table Address Counter Programming the Programmable Clock Programmable Clock Interrupt Control RegisterIL2-0 IREProgrammable Clock General Control Register PS2-0CLR Programmable Clock Timer Register PLSLocal Bus to IndustryPack Addressing Bit Memory SpaceComments Local Bus to IndustryPack Addressing $00FFFFFB $7FFFFD IPa I/O Space IPA6-0 CommentsIPab I/O Space IPa ID Space IPA5-0 CommentsMemory Space Accesses IP to Local Bus Data RoutingThis section shows data routing from an IP to the local bus IP to Local Bus Data Routing ID Space Accesses Space Lbsize LBA IPAFeatures MceccPerformance Mcecc Specifications Descriptions SpecificationsECC Cycle TypesError Reporting Single Bit Error Cycle Type = Burst Read or Non-Burst ReadDouble Bit Error Cycle Type = Burst Read or Non-Burst Read Single Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Non-Burst WriteTriple or Greater Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = ScrubError Logging Double Bit Error Cycle Type = ScrubTriple or Greater Bit Error Cycle Type = Scrub ScrubChip Defaults RefreshArbitration Programming Model Mcecc Internal Register Memory Map, Part Mcecc Base Address = $FFF43000 1st $FFF43100 2ndRegister Offset NameBase BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Address Register Bit Names D31 D30 D29 D28 D27 D26 D25 D24Scrub SAC7 SAC6 SAC5 SAC4 Addr Cntr 1st $FFF43000/2nd $FFF43100 8-bits Memory Configuration Register MSIZ2-MSIZ0Dummy Register RB3 Read Bit 3 is a read only bit that is alwaysRB4 Read Bit 4 is a read only bit that is always Base Address Register Difference from MEMC040 noneBit assignments for the Base Address Register are Bit assignments for the Dram Control Register are RWB3 Read/Write Bit 3 is a general purpose read/write bitRWB5 Read/Write Bit 5 is a general purpose read/write bit Bclk Frequency Register Data Control Register Mcecc Scrub Control Register Scrub Period Register Bits This register contains bits 7-0 of the Scrub Period RegisterChip Prescaler Counter Scrub Time On/Time Off RegisterSTOFF2-STOFF0 STON2-STON0 Scrubber Time OffScrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF4304C/2nd $FFF4314C 8-bits Error Logger Register Error Address Bits 1st $FFF43064/2nd $FFF43164 8-bits Error Syndrome Register Defaults RegisterRSIZ2-RSIZ0 SELI1, SELI0 Dram Array SizeRegister Base Address RESST2-RESST0 NocacheInitialization Mcecc Bank in Error Bit in Error Syndrome Code Syndrome DecodeBank C Bank a Mcecc Motorola Computer Group Documents Document Title Motorola Publication NumberLiterature Updates Manufacturers’ DocumentsTable A-2. Manufacturers’ Documents Table A-2. Manufacturers’ Documents Related Documentation BUsing Interrupts on the MVME172 VMEchip2 Tick Timer 1 Periodic Interrupt ExampleStep Register and Address Action and Reference Refer to the Vector Base RegisterUsing Interrupts on the MVME172 Page Index IN-2 DMA Gcsr Lanc IN-6 MPU SCC Scsi Mcecc IN-10 IN-11 Index MVME172 Programmer’s Reference Guide MVME172