Contents

CHAPTER 1 Board Description and Memory Maps

 

Introduction

1-1

Overview

1-1

Requirements

1-4

Block Diagrams

1-5

Functional Description

1-5

No-VMEbus-Interface Option

1-5

VMEbus Interface and VMEchip2

1-9

Memory Maps

1-9

Local Bus Memory Map

1-9

Normal Address Range

1-9

Detailed I/O Memory Maps

1-21

BBRAM/TOD Clock Memory Map

1-40

Interrupt Acknowledge Map

1-46

VMEbus Memory Map

1-46

VMEbus Accesses to the Local Bus

1-47

VMEbus Short I/O Memory Map

1-47

Software Support Considerations

1-47

Interrupts

1-47

Cache Coherency

1-48

Sources of Local BERR*

1-48

Local Bus Time-out

1-48

VMEbus Access Time-out

1-49

VMEbus BERR*

1-49

Local DRAM Parity Error

1-49

VMEchip2

1-49

Bus Error Processing

1-49

Description of Error Conditions on the MVME172

1-50

MPU Parity Error

1-50

MPU Off-board Error

1-51

MPU TEA - Cause Unidentified

1-51

MPU Local Bus Time-out

1-51

DMAC VMEbus Error

1-52

DMAC Parity Error

1-52

DMAC Off-board Error

1-53

DMAC LTO Error

1-53

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Motorola MVME172 manual Contents