LCSR Programming Model

Miscellaneous Control Register

ADR/SIZ

 

 

 

$FFF4008C (8 bits of 32)

 

 

BIT

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

NAME

MPIRQEN

 

REVEROM

DISSRAM

DISMST

NOELBBSY

DISBSYT

ENINT

DISBGN

 

 

 

 

 

 

 

 

 

 

OPER

R/W

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

RESET

0 PSL

 

0 PSL

0 PSL

0 PS

0 PS

0 PS

0 PS

0 PS

 

 

 

 

 

 

 

 

 

 

 

DISBGN

When this bit is high, the VMEbus BGIN filters are

 

 

 

disabled. When this bit is low, the VMEbus BGIN filters

 

 

 

are enabled. This bit should not be set.

 

 

 

ENINT

When this bit is high, the local bus interrupt filters are

 

 

 

enabled. When this bit is low, the local bus in- terrupt

 

 

 

filters are disabled. This bit should not be set.

 

DISBSYT When this bit is low, the minimum VMEbus BBSY* time when the local bus master has been retried off the local bus is 32 local bus clocks. When this bit is high, the minimum VMEbus BBSY* time when the local bus master has been retried off the local bus is 3 local bus clocks.

When a local bus master attempts to access the VMEbus and a VMEbus master attempts to access the local bus, a deadlock is created. The VMEchip2 detects this condition and requests the local bus master to give up the local bus and retry the cycle. This allows the VMEbus master to complete the cycle to the local bus. If the VMEchip2 receives VMEbus mastership, the local master has not returned from the retry, and this bit is high, VMEchip2 drives VMEbus BBSY* for the minimum time (about 90 ns) and then releases the VMEbus. If the local master does not return from the retry within this 90 ns window, the board loses its turn on the VMEbus. If the VMEchip2 receives VMEbus mastership, the local master has not returned from the retry, and this bit is low, VMEchip2 drives VMEbus BBSY* for a minimum of 32 local bus clocks, which allows the local bus master time to return

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Page 177
Image 177
Motorola MVME172 manual Miscellaneous Control Register, Enint