Motorola MVME172 manual Pls, Programmable Clock Timer Register

	Programming Model
	enabling/disabling the pre-scaler’s counter. Note that
	clearing EN does not clear any of the programmable
	clock’s registers.
PLS	When PLS is set, the programmable clock output is
	asserted for one BCK period. When PLS is cleared, the
	programmable clock output toggles creating a square
	wave.
PLTY	PLTY controls the polarity of the programmable clock
	output. When PLTY is cleared, the negated (and cleared)
	state of the output is a logic 0, and the asserted state is a
	logic 1. When PLTY is set, the opposite is true.

Programmable Clock Timer Register

ADR/SIZ		$FFFBC082 (16 bits)
BIT	15	...	0
NAME		Programmable Clock Timer Register
OPER		R/W
RESET		0 R

When enabled, the programmable clock timer counter increments until it matches the value contained in this register, at which time it rolls over and resumes counting. The effect is that the frequency of the programmable clock output is the frequency of the (pre-scaleroutput)/(the-value-in-this- register + 1). For example, if the PLS bit is cleared, PLS2-0 are %000, and the timer register contains $0001, then the programmable clock output frequency is BCK/4 = 8 MHz if BCK = 32 MHz. For the pulsed output, the formula for the period of the frequency of the recurring pulse is 1/((pre- scaler output)/ (the-value-in-this-register+ 1)). For example, if the PLS bit is set, PLS2-0 are %001, and the timer register contains $0001, then the programmable clock frequency of the pulsed output is BCK/4 = 8 MHz if BCK = 32 MHz.

4

http://www.mcg.mot.com/literature 4-45