Motorola DSP56301 user manual Timer Control/Status Register TCSR0$FFFF8F Read/Write

Models: DSP56301

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Programming Sheets

Application:

 

 

Date:

 

 

 

 

 

Programmer:

 

Sheet 2 of 3

Timers

Inverter Bit 8

0= 0- to-1 transitions on TIO input increment the counter, or high pulse width measured, or high pulse output on TIO

1= 1-to-0 transitions on TIO input increment the counter, or low pulse width measured, or low pulse output on TIO

Timer Reload Mode Bit 9

0 = Timer operates as a free running counter

1 = Timer is reloaded when selected condition occurs

Direction Bit 11

0 = TIO pin is input

1 = TIO pin is output

Data Input Bit 12

0 = Zero read on TIO pin

1 = One read on TIO pin

Data Output Bit 13

0 = Zero written to TIO pin

1 = One written to TIO pin

Prescaled Clock Enable Bit 15

0 = Clock source is CLK/2 or TIO

1 = Clock source is prescaler output

Timer Compare Flag Bit 21

0 = “1” has been written to TCSR(TCF), or timer compare interrupt serviced

1 = Timer Compare has occurred

Timer Overflow Flag Bit 20

0 = “1” has been written to TCSR(TOF), or timer Overflow interrupt serviced

1 = Counter wraparound has occurred

Timer Control Bits 4–7 (TC[3–0])

 

TC (3:0)

TIO

Clock

Mode

 

 

 

 

 

 

 

0000

GPIO

Internal

Timer

 

0001

Output

Internal

Timer Pulse

 

0010

Output

Internal

Timer Toggle

 

0011

Input

External

Event Counter

 

0100

Input

Internal

Input Width

 

0101

Input

Internal

Input Period

 

0110

Input

Internal

Capture

 

0111

Output

Internal

Pulse Width Modulation

 

1000

 

Reserved

 

1001

Output

Internal

Watchdog Pulse

 

1010

Output

Internal

Watchdog Toggle

 

1011

 

Reserved

 

1100

 

Reserved

 

1101

 

Reserved

 

1110

 

Reserved

 

1111

 

Reserved

 

 

 

 

 

 

Timer Enable Bit 0

0 = Timer Disabled

1 = Timer Enabled

Timer Overflow Interrupt Enable Bit 1

0 = Overflow Interrupts Disabled

1 = Overflow Interrupts Enabled

Timer Compare Interrupt Enable Bit 2

0 = Compare Interrupts Disabled

1 = Compare Interrupts Enabled

23

22

21

20

 

19

18

17

16

 

15

14

13

12

 

11

10

9

8

 

 

7

6

5

4

 

3

2

1

0

 

 

 

 

 

*0

*0

TCF

TOF

 

*0

*0

*0

*0

 

PCE

*0

DO

DI

 

DIR

*0

TRM

INV

 

 

TC3

TC2

TC1

TC0

 

*0

TCIE

TQIE

TE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer Control/Status Register

 

TCSR0:$FFFF8F Read/Write

 

 

 

 

 

 

 

 

 

Reset = $000000

 

 

 

 

TCSR1:$FFFF8B Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCSR2:$FFFF87 Read/Write

 

 

 

 

 

 

 

 

 

*= Reserved, Program as 0

Figure B-26.Timer Control/Status Register (TCSR)

B-38

DSP56301 User’s Manual

Page 350
Image 350
Motorola DSP56301 Timer Control/Status Register TCSR0$FFFF8F Read/Write, TCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write