Index-14 DSP56301 User’s Manual

Zero (Z) 4-11

Extended Mode Register (EMR) 4-7Arithmetic Saturation Mode (SM) 4-7Cache Enable (CE) 4-8

Core Priority (CP) 4-7

DO FOREVER (FV) Flag 4-8Instruction Cache Enable (CE) 4-7Rounding Mode (RM) 4-7Sixteen-bit Arithmetic Mode (SA) 4-8

Mode Register (MR) 4-7Do Loop Flag (LF) 4-8

Double-Precision Multiply Mode (DM) 4-9Interrupt Mask (I) 4-10

Scaling (S) Mode 4-10

Sixteen-bit Compatibility (SC) Mode 4-9programming sheet B-13

Status/Command Configuration Register (CSTR/CCMR) 6-64

Data Parity Reported (DPR) 6-65

Detected Parity Error (DPE) 6-65

DEVSEL Timing (DST[1–0]) 6-65

Fast Back-to-Back Capable (FBBC) 6-66Parity Error Response (PERR) 6-66PCI Bus Master Enable (BM) 6-66

PCI Memory Space Enable (MSE) 6-66Received Master Abort (RMA) 6-65Received Target Abort (RTA) 6-65Signaled System Error (SSE) 6-65Signalled Target Abort (STA) 6-65System Error Enable (SERE) 6-66Wait Cycle Control (WCC) 6-66

Stop Delay Mode (SD) bit 4-15STOP instruction 6-12,8-6STOP reset 6-12

Switch mode 1-5

switching memory configuration dynamically 3-5switching memory sizes 3-2

Synchronous mode 7-10,7-11,7-13,8-2,8-18Synchronous Serial Interface Status Register

(SSISR) 7-14,7-28

Receive Data Register Full (RDF) 7-28

Receiver Frame Sync Flag (RFS) 7-29Receiver Overrun Error Flag (ROE) 7-28Serial Input Flag 0 (IF0) 7-29

Serial Input Flag 1 (IF1) 7-29

Transmit Data Register Empty (TDE) 7-28Transmit Frame Sync Flag (TFS) 7-29Transmitter Underrun Error Flag (TUE) 7-28

Synchronous/Asynchronous (SYN) bit 7-21System Error Enable (SERE) bit 6-66system initialization 5-1

SZ register 1-8

TA Synchronize Select (TAS) bit 4-14Target Wait State Disable (TWSD) bit 6-49Test Access Port (TAP) 1-5,1-9

signals 2-29

Test Clock (TCK) 2-29Test Data Input (TDI) 2-29Test Data Output (TDO) 2-29Test Mode Select (TMS) 2-29Test Reset (TRST 2-29Time Slot Register (TSR) 7-33timer 2-2,2-27

after Reset 9-3enabling 9-4exception 9-4

Compare 9-4

Overflow 9-4GPIO 5-7initialization 9-3operating modes 9-5

Capture (mode 6) 9-5,9-14,9-18

Event Counter (mode 3) 9-5,9-12GPIO (mode 0) 9-5,9-6

Input Period (mode 5) 9-5,9-14,9-16Input Width (mode 4) 9-5,9-14overview 9-6

Pulse (mode 1) 9-5,9-8

Pulse Width Modulation (PWM) (mode 7) 9-5,9-14,9-19

reserved 9-25setting 9-4

signal measurement modes 9-14Toggle (mode 2) 9-5,9-10watchdog modes 9-21

Watchdog Pulse (mode 9) 9-5,9-22Watchdog Toggle (mode 10) 9-5,9-22

prescaler counter 9-25programming model 9-25signals 2-1

special cases 9-25

timer compare interrupts 9-32

Timer Compare Register (TCPR) 9-34Timer Control/Status Register (TCSR) 9-28

Data Input (DI) 9-29Data Output (DO) 9-29Direction (DIR) 9-30Inverter (INV) 9-30,9-32Prescaler Clock Enable (PCE) 9-29Timer Compare Flag (TCF) 9-29

Timer Compare Interrupt Enable (TCIE) 9-32Timer Control (TC) 9-31

Timer Enable (TE) 9-32

Timer Overflow Flag (TOF) 9-29

Index-14

DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola user manual Index-14 DSP56301 User’s Manual

Models: DSP56301

Index-14

DSP56301 User’s Manual

DSP56301 specifications