Host-Side Programming Model

read/write command is in progress and the PCI address is $04. In Self-Configuration mode (DCTR[DCTR[HM]] = $5), the DSP56300 core can indirectly access the CCMR (see Section 6.5.5, Self-Configuration Mode (DCTR[HM] = $5), on page 6-16). The host writes to CSTR/CCMR in accordance with the byte enables. Byte lanes that are not enabled are not written, and the corresponding bits remain unchanged. The host can access CSTR/CCMR only in PCI mode (DCTR[HM]≠$1).

Table 6-26.Status/Command Configuration Register (CSTR/CCMR) Bit Definitions

Bit Number

Bit Name

Reset Value

 

Description

 

 

 

 

 

 

 

 

31

DPE

0

Detected Parity Error

 

 

 

Indicates that the HI32 hardware has detected a parity error. In PCI

 

 

 

mode (DCTR[HM] = $1), DPE is set when the HI32 detects either an

 

 

 

address or data parity error. DPE is cleared when the host processor

 

 

 

writes a value of one to it. The personal hardware reset clears DPE.

 

 

 

 

30

SSE

0

Signaled System Error

 

 

 

Indicates a system error. In PCI mode (DCTR[HM] = $1), SSE is set

 

 

 

when the HI32 asserts the

HSERR

pin. SSE is cleared when the host

 

 

 

processor writes a value of one to it. The personal hardware reset

 

 

 

clears SSE.

 

 

 

 

29

RMA

0

Received Master Abort

 

 

 

Indicates a master-abort PCI bus state. In PCI mode (HM = $1), RMA is

 

 

 

set when the HI32, as a master device, terminates its transaction with

 

 

 

master-abort. RMA is cleared when the host processor writes a value of

 

 

 

one to it. The personal hardware reset clears RMA.

 

 

 

 

28

RTA

0

Received Target Abort

 

 

 

Indicates a target-abort PCI bus event. In PCI mode (DCTR[HM] = $1),

 

 

 

RTA is set when the HI32, as a master device, detects that its

 

 

 

transaction is terminated with target-abort. RTA is cleared when the

 

 

 

host processor writes a value of one to it. The personal hardware reset

 

 

 

clears RTA.

 

 

 

 

27

STA

0

Signalled Target Abort

 

 

 

Indicates a target-abort PCI bus event. In PCI mode (DCTR[HM] = $1),

 

 

 

STA is set when the HI32, as a target device, terminates a transaction

 

 

 

with target-abort. STA is cleared when the host processor writes a value

 

 

 

of one to it. The personal hardware reset clears STA.

 

 

 

 

26–25

DST[1–0]

0

DEVSEL Timing (hardwired to $1)

 

 

 

Encode the timing of the HDEVSEL pin in PCI mode (DCTR[HM] = $1).

 

 

 

DST[1–0] are hardwired to DST = $1, indicating that the HI32 belongs

 

 

 

to the medium DEVSEL timing class of the PCI devices.

 

 

 

 

24

DPR

0

Data Parity Reported

 

 

 

Indicates the detection of a data parity error in PCI mode (DCTR[HM] =

 

 

 

$1). The DPR is set when the HI32 acts as a bus master and detects a

 

 

 

data parity error or samples HPERR asserted while CCMR[PERR] is

 

 

 

set. DPR is cleared when the host processor writes a value of one to it.

 

 

 

The personal hardware reset clears DPR.

 

 

 

 

 

 

Host Interface (HI32)

6-65

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Motorola DSP56301 user manual Detected Parity Error, Signaled System Error, Received Master Abort, Received Target Abort
Page 182 Page 184

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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