Master Wait State Disable, Force, Hserr | Motorola DSP56301 instruction

HI32 DSP-Side Programming Model

Table 6-11.DSP PCI Control Register (DPCR) Bit Definitions (Continued)

Bit Number	Bit Name	Reset Value						Description

19	MWSD	0	Master Wait State Disable
			Disables PCI wait states (inserted by deasserting						HIRDY)	during a data
			phase. When MWSD is cleared, the HI32 as the active PCI master
			(DCTR[HM] = $1) inserts wait states to extend the current data phase if
			it cannot guarantee the completion of the next data phase. The HI32
			asserts HIRDY and completes the current data phase when one of the
			following is true:
			ν it can complete the next data phase
			ν it determines to terminate the transaction due to time-out or
			completion
			If MWSD is set, the HI32, as the active PCI master (DCTR[HM] = $1),
			does not insert wait states. If it cannot guarantee the completion of the
			next data phase, the HI32 completes the current data phase and
			terminates the transaction. MWSD is ignored when the HI32 is not in
			the PCI mode (DCTR[HM]≠$1). The value of MWSD can change only
			when DSR[HACT] = 0.

18	MACE	0	Master Access Counter Enable
			Enables/disables the master access counter. When the master access
			counter is enabled, the HI32, as the active PCI master (DCTR[HM] =
			$1), terminates the current PCI transaction when the counter reaches
			the terminal count. When MACE is cleared, the counter is disabled and
			the burst length of HI32-initiated transactions is unlimited. To terminate
			an HI32-initiated transaction, the DSP56300 core writes a value of one
			to the DPCR[MTT] bit. MACE is ignored when the HI32 is not in PCI
			mode (DCTR[HM]≠$1). The value of MACE can change only if MARQ =
			1 or DSR[HACT] = 0.

17		0	Reserved. Write to 0 for future compatibility.

16	SERF	0		Force
16	SERF	0	HSERR	Force
			Controls the		HSERR		pin state in PCI mode (DCTR[HM] = $1). When the
			core sets SERF and the HI32 is the current PCI bus master or a
			selected target, the			HSERR		pin is pulsed one PCI clock cycle. If the
			system error enable (SERE) bit is set in the Status/Command
			Configuration Register (CSTR/CCMR), the signalled system error
			(SSE) bit is set in the CSTR/CCMR. HI32 hardware clears SERF after
			HSERR is asserted. When SERF is cleared, HI32 hardware controls
			the HSERR pin. The DSP56300 core cannot write a value of zero to
			SERF. SERF is ignored when the SERE bit is cleared or when the HI32
			is not an active PCI agent (that is, DCTR[HM]≠$1 or the HI32 is not the
			current PCI bus master or a selected target).

15	MTT	0	Master Transfer Terminate
			Generates a transaction termination initiated by the PCI master. In PCI
			mode (DCTR[HM] = $1), when the HI32 is the active PCI master and
			the DSP56300 core sets the MT bit, a master- initiated transaction
			termination (not master-abort) is generated. HI32 hardware clears MTT
			when the PCI bus is in the idle state. The DSP56300 core cannot write
			a value of zero to MTT. MTT is ignored when the HI32 is not in the PCI
			mode (DCTR[HM]≠$1).

6-28	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Master Wait State Disable, Master Access Counter Enable, Force, Hserr

Models: DSP56301

Table 6-11.DSP PCI Control Register (DPCR) Bit Definitions (Continued)

Master Wait State Disable

Master Access Counter Enable

Force

HSERR

Master Transfer Terminate

DSP56301 specifications