Motorola DSP56301 user manual Program Control Unit PCU

DSP56300 Core Functional Blocks

arithmetic used in the address register update calculation. The modifier value is decoded in the address ALU.

1.4.3Program Control Unit (PCU)

The PCU prefetches and decodes instructions, controls hardware DO loops, and processes exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300 core. The PCU consists of three hardware blocks:

νProgram decode controller — decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control.

νProgram address generator — contains all the hardware needed for program address generation, system stack, and loop control.

νProgram interrupt controller — arbitrates among all interrupt requests (internal interrupts, as well as the five external requests IRQA, IRQB, IRQC, IRQD, and NMI), and generates the appropriate interrupt vector address.

PCU features include the following:

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Position-independent code support

Addressing modes optimized for DSP applications (including immediate offsets)

On-chip instruction cache controller

On-chip memory-expandable hardware stack

Nested hardware DO loops

Fast auto-return interrupts

Hardware system stack

The PCU uses the following registers:

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Program counter register

Status register

Loop address register

Loop counter register

Vector base address register

Size register

Stack pointer

Operating mode register

Stack counter register

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