Motorola DSP56301 user manual Bus Command/Byte Enable Host Address Bus, Reserved

Host Interface (HI32)

Table 2-12.Host Port Pins (HI32) (Continued)

Signal			PCI			Universal Bus Mode
Name
					Enhanced Universal Bus Mode			GPIO
HP[18–16]					HA[2–0]			HIO[18–16]
		HC3/HBE3–HC0/HBE0
	Bus Command/Byte Enable				Host Address Bus			GPIO2
	Tri-state bidirectional bus.				Input pin.
	During the address phase of a				Selects HI32 register to access. HA[10–3]
					select the HI32 and HA[2–0] select the
	transaction, HC3/HBE3–HC0/HBE0
	define the bus command. During the				particular register of the HI32 to be accessed.
	data phase HC3/HBE3–HC0/HBE0
HP19					Reserved			HIO19
	are used as byte enables. The byte
							or GND.	GPIO2
HC3/HBE3					Must be forced or pulled to V
	enables determine which byte lanes
							CC
	carry meaningful data.
HP20
	HTRDY				HDBEN
	Host Target Ready				Host Data Bus Enable			HIO20
	Sustained tri-state bidirectional pin.2				Output pin.			GPIO2
	Indicates the target agent’s ability to				Asserted during HI32 accesses.
	complete the current data phase of				When asserted the external (optional) data
	the transaction. HTRDY is used in				transceiver outputs are enabled. When
	conjunction with HIRDY. When a data				deasserted the external transceiver outputs
	phase is completed on any clock both				are high impedance.
	HIRDY and HTRDY are sampled
	asserted. HTRDY is asserted if:
	ν during a data read valid data is
		present on HAD31-HAD0
		(HRRQ=1 in the HSTR).
	ν during a data write it indicates
		the HI32 is ready to accept
		data (HTRQ=1 in the HSTR).
	ν during a vector write it indicates
		the HI32 is ready to accept a
		new host command (HC=0 in
		the HCVR).
	Wait cycles are inserted until			HIRDY
	and HTRDY are asserted together.
HP21
	HIRDY				HDBDR
	Host Initiator Ready				Host Data Bus Direction			HIO21
	Sustained tri-state bidirectional pin.2				Output pin.			GPIO2
	Indicates the initiating agent’s ability				Driven high on write data transfers and driven
	to complete the current data phase of				low on read data transfers. This pin is
	the transaction. Used with HTRDY.				normally high.
	When a data phase is completed on
	any clock both HIRDY and HTRDY
	are sampled asserted. Wait cycles are
	inserted until both HIRDY and HTRDY
	are asserted together. The HI32
	deasserts HIRDY if it cannot complete
	the next data phase.

Signals/Connections 2-17