Motorola DSP56301 user manual DSP Control Register Dctr Read/Write Address X FFFFC5, Application

Programming Sheets

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Sheet 1 of 10

Host Processor (HI32)

HI32 Mode, Bits 22–20

Host Transfer Acknowledge Polarity, Bit 15

Control HI32 operating modes, as follows:

0 = HTA is active high

1 = HTA is active low

000

Terminate and Reset

001

PCI

Host Read/Write Polarity, Bit 14

010

Universal Bus

0 = Host-to-DSP direction is low HRW

011

Enhanced Universal Bus

1 = Host-to-DSP direction is high HRW

100

GPIO

101

Self-Configuration

Host Data Strobe Mode, Bit 13

110

Reserved

0 = Double-Strobe pin mode is selected

111

Reserved

1 = Single-strobe pin mode is selected

Host Interrupt Request Drive Control, Bit 19

Host Interrupt A, Bit 6

0 = HINTA pin released

0 = HIRQ pin is an open-drain output

1 = HINTA pin driven low

1 = HIRQ pin is always driven

Host Flags, Bits 5–3

Host Interrupt Request Handshake Mode, Bit 18

Used for DSP-to-host communication

0 = HIRQ is asserted for specified number of core

Set or cleared by DSP, visible to host

clock cycles, which is set in the CLAT[LT]

1 =

HIRQ

is deasserted when interrupt request

source is cleared

Slave Receive Interrupt Enable, Bit 2

0 = SRRQ interrupt requests are disabled

Host Reset Polarity, Bit 17

1 = Core interrupt when DSR[SRRQ] is set

		0 = HRST pin is active high and the HI32 is reset
		if the HRST pin is high												Slave Transmit Interrupt Enable, Bit 1
		1 = HRST pin is active low and the HI32 is reset
														0 = STRQ interrupt requests are disabled
		if the HRST pin is low
														1 = Core interrupt when DSR[STRQ] is set
			Host DMA Request Polarity, Bit 16											Host Command Interrupt Enable, Bit 0
			0 = HDRQ pin is active high
			1 = HDRQ pin is active low											0 = HCP interrupt requests are disabled
														1 = Core interrupt when DSR[HCP] is set
23	22	21	20	19	18	17	16	15	14	13	12 11 10	9	8	7	6	5	4	3	2	1	0

*0

HM2

HM1

HM0 HIRD

HIRH

HRSP

HDRPHRWP

HRWP

HDSM

*0 *0

*0

*0

*0 *0

HINT

HF5

HF4 HF3

SRIE

STIE

HCIE

DSP Control Register (DCTR) Read/Write Address: X: FFFFC5

= Reserved, Program as 0

Reset = $000000

Note: All bits but the mode setting bits (Bits 22–20) work only in a Universal Bus Mode*

(DCTR[HM] = $2 or $3)

Figure B-10.DSP Control Register (DCTR)

B-22 DSP56301 User’s Manual