Index-4 DSP56301 User’s Manual

PCI Host Data Transfer Complete (HDTC) 6-39PCI Master Abort (MAB) 6-40

PCI Master Address Request (MARQ) 6-40

PCI Master Receive Data Request (MRRQ) 6-41PCI Master Transmit Data Request (MTRQ) 6-41PCI Master Wait States (MWS) 6-41

PCI Target Abort (TAB) 6-40

PCI Target Disconnect (TDIS) 6-40PCI Target Retry (TRTY) 6-39

PCI Time Out Termination (TO) 6-39Remaining Data Count (RDC[5–0]) 6-38Remaining Data Count Qualifier (RDCQ) 6-38

DSP PCI Transaction Address (High) (AR[31–16]) bits 6-32

DSP PCI Transaction Address (Low) (AR[15–0]) bits 6-34

DSP Receive Data FIFO (DRXR) 6-41

DSP Slave Transmit Data Register (DTXS) 6-7,6-42DSP Status Register (DSR)

HI32 Active (HACT) 6-35

Host Command Pending (HCP) 6-37Host Flags 2–0 (HF[2–0]) 6-36

Slave Receive Data Request (SRRQ) 6-36Slave Transmit Data Request (STRQ) 6-37

DSP56000

code compatibility 1-4DSP56300

code compatibility 1-4core 1-1

Family Manual 1-1,1-4DSP56301

Technical Data 1-1DSP56301 Operating Modes 4-2

dynamic memory configuration switching 3-5

Enhanced Synchronous Serial Interface (ESSI) 1-5,2-2,2-23,2-25,7-1

24-bit fractional data 7-16after reset 7-6

Asynchronous mode 7-4,7-11,7-20audio enhancements 7-2

byte format 7-13

clock generator 7-11,7-17Clock Sources 7-3codec 7-13

control and time slot registers 7-6control direction of SC2 I/O signal 7-23Control Register A (CRA)

Alignment Control (ALC) 7-16

Frame Rate Divider Control (DC) 7-16Prescale Modulus Select (PM) 7-16Prescaler Range (PSR) 7-16

programming sheet B-32Select SCK (SSC1) 7-15Word Length Control (WL) 7-15

Control Register B (CRB) Clock Polarity (CKP) 7-22

Clock Source Directions (SCKD) 7-22Frame Sync Length (FSL) 7-22Frame Sync Polarity (FSP) 7-22Frame Sync Relative Timing (FSR) 7-22Mode Select (MOD) 7-21programming sheet B-33

Receive Enable (RE) 7-20

Receive Exception Interrupt Enable (REIE) 7-19Receive Interrupt Enable (RIE) 7-19

Receive Last Slot Interrupt Enable 7-19

Serial Control Direction 0 (SCD0) 7-23

Serial Control Direction 1 (SCD1) 7-23

Serial Control Direction 2 (SCD2) 7-23Serial Output Flag 0 (OF0) 7-23Serial Output Flag 1 (OF1) 7-23

Shift Direction (SHFD) 7-22Synchronous/Asynchronous (SYN) 7-21Transmit 0 Enable (TE0) 7-20Transmit 1 Enable (TE1) 7-21Transmit 2 Enable (TE2) 7-21Transmit Exception Interrupt Enable

(TEIE) 7-19

Transmit Interrupt Enable (TIE) 7-20

Transmit Last Slot Interrupt Enable (TLIE) 7-19control registers 7-14

data and control signals 7-3DMA 7-7

exception configuration 7-9exceptions 7-7

receive last slot interrupt 7-8transmit data 7-8

transmit data with exception status 7-8transmit last slot interrupt 7-8

flags 7-13

frame rate divider 7-10frame sync

generator 7-17length 7-12polarity 7-12selection 7-11signal 7-7,7-10,7-18word length 7-12

initialization 7-6initialization example 7-7

internally generated clock and frame sync 7-7interrupt 7-7

Interrupt Service Routine (ISR) 7-9interrupt trigger event 7-9multiple serial device selection 7-4

Index-4

DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola user manual Index-4 DSP56301 User’s Manual

Models: DSP56301

Index-4

DSP56301 User’s Manual

DSP56301 specifications