Host Interface (HI32)

Table 2-12.Host Port Pins (HI32) (Continued)

Signal

 

 

 

PCI

 

 

 

 

Universal Bus Mode

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enhanced Universal Bus Mode

GPIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HP29

 

 

 

 

 

 

 

 

 

disconnected

 

HSTOP

 

 

 

HWR/HRW

 

 

Host Stop

 

Host Write/Read-Write

 

 

 

Sustained tri-state bidirectional pin.2

 

Schmitt trigger input pin.

 

 

 

Indicates that the current target is

 

When in the double-strobe mode of the HI32

 

 

 

requesting the master to stop the

 

(HDSM=0), this pin functions as host write

 

 

 

current transaction.

 

input strobe (HWR). The host processor

 

 

 

 

 

 

 

initiates a write access by asserting HWR.

 

 

 

 

 

 

 

Data input is latched with the rising edge of

 

 

 

 

 

 

 

HWR.

 

 

 

 

 

 

 

In the single-strobe mode of the HI32

 

 

 

 

 

 

 

(HDSM=1), this pin functions as host

 

 

 

 

 

 

 

read-write (HRW) input. It selects the direction

 

 

 

 

 

 

 

of data transfer for each host processor

 

 

 

 

 

 

 

access: from the HI32 to the host processor

 

 

 

 

 

 

 

when HRW is asserted and from the host

 

 

 

 

 

 

 

processor to the HI32 when HRW is

 

 

 

 

 

 

 

deasserted. The polarity of the HRW pin is

 

 

 

 

 

 

 

controlled by HRWP bit in the DCTR.

 

 

 

 

 

 

 

NOTE: Simultaneous assertion of HRD and

 

 

 

 

 

 

 

HWR is illegal.

 

HP30

HIDSEL

 

 

 

 

 

disconnected

 

HRD/HDS

 

 

Initialization Device Select

 

Host Read/Data Strobe

 

 

 

Input pin.

 

Schmitt-trigger input pin.

 

 

 

Used as a chip select in lieu of the

 

In the double-strobe mode of the HI32

 

 

 

upper 21 address lines during

 

(HDSM=0), this pin functions as the host read

 

 

 

configuration read and write

 

strobe (HRD). The host processor initiates a

 

 

 

transactions.

 

read access by asserting HRD. Data output

 

 

 

 

 

 

 

may be latched with the rising edge of HRD.

 

 

 

 

 

 

 

In the single-strobe mode of the HI32

 

 

 

 

 

 

 

(HDSM=1), this pin functions as the host data

 

 

 

 

 

 

 

strobe (HDS). The host processor initiates a

 

 

 

 

 

 

 

read access by asserting HDS with HRW

 

 

 

 

 

 

 

asserted. Data output may be latched with the

 

 

 

 

 

 

 

rising edge of HDS. The host processor

 

 

 

 

 

 

 

initiates a write access by asserting HDS with

 

 

 

 

 

 

 

HRW deasserted. Data input is latched by the

 

 

 

 

 

 

 

HI32 with the rising edge of HDS.

 

 

 

 

 

 

 

NOTE: Simultaneous assertion of HRD and

 

 

 

 

 

 

 

HWR is illegal.

 

HP31

 

 

 

 

 

Reserved.

disconnected

 

HFRAME

 

 

 

 

Host Cycle Frame

 

Must be forced or pulled up to VCC.

 

 

 

Sustained tri-state bidirectional pin.2

 

 

 

 

 

 

 

 

Driven by the current master to

 

 

 

 

 

 

 

 

indicate the beginning and duration of

 

 

 

 

 

 

 

 

an access. HFRAME is deasserted in

 

 

 

 

 

 

 

 

the final data phase of the transaction.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-20

DSP56301 User’s Manual

Page 50
Image 50
Motorola DSP56301 user manual Hstop HWR/HRW, Host Stop Host Write/Read-Write, Hrd/Hds, Host Cycle Frame

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.