Motorola DSP56301 Hstop HWR/HRW, Host Stop Host Write/Read-Write, Hrd/Hds, Host Cycle Frame

Host Interface (HI32)

Table 2-12.Host Port Pins (HI32) (Continued)

Signal			PCI			Universal Bus Mode
Name
					Enhanced Universal Bus Mode		GPIO
HP29							disconnected
		HSTOP		HWR/HRW
		Host Stop		Host Write/Read-Write
		Sustained tri-state bidirectional pin.2		Schmitt trigger input pin.
		Indicates that the current target is		When in the double-strobe mode of the HI32
		requesting the master to stop the		(HDSM=0), this pin functions as host write
		current transaction.		input strobe (HWR). The host processor
				initiates a write access by asserting HWR.
				Data input is latched with the rising edge of
				HWR.
				In the single-strobe mode of the HI32
				(HDSM=1), this pin functions as host
				read-write (HRW) input. It selects the direction
				of data transfer for each host processor
				access: from the HI32 to the host processor
				when HRW is asserted and from the host
				processor to the HI32 when HRW is
				deasserted. The polarity of the HRW pin is
				controlled by HRWP bit in the DCTR.
				NOTE: Simultaneous assertion of HRD and
				HWR is illegal.
HP30	HIDSEL						disconnected
				HRD/HDS
		Initialization Device Select		Host Read/Data Strobe
		Input pin.		Schmitt-trigger input pin.
		Used as a chip select in lieu of the		In the double-strobe mode of the HI32
		upper 21 address lines during		(HDSM=0), this pin functions as the host read
		configuration read and write		strobe (HRD). The host processor initiates a
		transactions.		read access by asserting HRD. Data output
				may be latched with the rising edge of HRD.
				In the single-strobe mode of the HI32
				(HDSM=1), this pin functions as the host data
				strobe (HDS). The host processor initiates a
				read access by asserting HDS with HRW
				asserted. Data output may be latched with the
				rising edge of HDS. The host processor
				initiates a write access by asserting HDS with
				HRW deasserted. Data input is latched by the
				HI32 with the rising edge of HDS.
				NOTE: Simultaneous assertion of HRD and
				HWR is illegal.
HP31				Reserved.			disconnected
		HFRAME
		Host Cycle Frame		Must be forced or pulled up to VCC.
		Sustained tri-state bidirectional pin.2
		Driven by the current master to
		indicate the beginning and duration of
		an access. HFRAME is deasserted in
		the final data phase of the transaction.

2-20 DSP56301 User’s Manual