HI32 Programming Model/Quick Reference

HI32 Registers—Quick Reference

Reg

 

 

Bit

 

 

 

 

Comments

Reset Type

 

 

 

 

 

 

 

 

 

 

Num

Mnemonic

Name

Val

Function

HS

PH

PS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HCVR

 

HC

Host Command

0

no host command pending

cleared when

-

-

0

 

0

 

 

1

host command pending

the HC interrupt

 

 

 

 

 

 

 

 

 

 

request is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

serviced

 

 

 

 

7-1

HV[6–0]

Host Command Vector

 

 

 

 

default vector

-

default

-

 

 

 

 

 

 

 

 

 

vector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HNMI

Host Non Maskable

0

a maskable interrupt request

 

-

0

-

 

15

 

Interrupt Request

1

a non-maskable interrupt

 

 

 

 

 

 

 

 

 

request

 

 

 

 

HRXM

31-0

 

Host Master Receive

 

 

 

 

 

 

empty

 

 

 

Data FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HRXS

31-0

 

Host Slave Receive

 

 

 

 

 

 

empty

 

 

 

Data FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HTXR

31-0

 

Host Transmit Data

 

 

 

 

 

 

empty

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CVID

15-0

VID[15–0]

Vendor ID

$

 

 

 

hardwired $1057

-

-

-

CDID

 

 

1057

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31-16

DID[15–0]

Device ID

$

 

 

 

hardwired $1801

-

-

-

 

 

 

1801

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCMR

 

MSE

Memory Space Enable

0

memory space response

 

-

0

-

CSTR

1

 

 

1

disabled

 

 

 

 

 

 

 

 

memory space response

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

enabled

 

 

 

 

 

2

BM

Bus Master Enable

0

HI32 PCI bus master disabled

 

-

0

-

 

 

 

1

HI32 PCI bus master enabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PERR

Parity Error Response

0

HI32 does not drive

 

 

 

-

0

-

 

 

HPERR

 

 

 

6

 

 

1

HI32 drives HPERR if a parity

 

 

 

 

 

 

 

 

 

error is detected

 

 

 

 

 

7

WCC

Wait Cycle Control

0

HI32 never executes address

hardwired 0

-

-

-

 

 

 

 

stepping

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SERE

System Error Enable

0

HI32 does not drive

 

 

 

-

0

-

 

8

HSERR

 

 

 

 

 

1

HI32 can drive HSERR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FBBC

Fast Back-to-Back

1

HI32 supports fast

hardwired 1

-

-

-

 

23

 

Capable

 

back-to-back transactions as

 

 

 

 

 

 

 

 

 

a target

 

 

 

 

 

 

DPR

Data Parity Reported

0

no parity error detected

cleared by

-

0

-

 

24

 

 

1

HI32 master parity error

writing 1

 

 

 

 

 

 

 

 

detected or HPERR asserted

 

 

 

 

 

26-25

DST[1–0]

DEVSEL Timing

01

medium DEVSEL timing

hardwired 01

-

-

-

 

 

STA

Signaled Target Abort

0

HI32 has not generated a

cleared by

-

0

-

 

27

 

 

1

target-abort event

writing 1

 

 

 

 

 

 

 

HI32 target, generated a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

target-abort event

 

 

 

 

 

 

RTA

Received Target Abort

0

HI32 has not received a

cleared by

-

0

-

 

28

 

 

1

target-abort event

writing 1

 

 

 

 

 

 

 

HI32 master, received a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

target-abort event

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Host Interface (HI32)

6-79

Page 196 Page 198
Page 197
Image 197
Motorola DSP56301 user manual Hcvr, Hnmi, Hrxm, Hrxs, Htxr, Fifo Cvid, Cdid, Ccmr MSE, Cstr, Perr, Dpr
Page 196 Page 198

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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