Timer Prescaler Load Register Tplr, PS1 PS0

Triple Timer Module Programming Model

9.4.2Timer Prescaler Load Register (TPLR)

The TPLR is a read/write register that controls the prescaler divide factor (that is, the number that the prescaler counter loads and begins counting from) and the source for the prescaler input clock.

PS1

PS0

PL20

PL19

PL18

PL17

PL16

PL15

PL14

PL13

PL12

PL11

PL10

PL9

PL8

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

— Reserved bit. Read as 0. Write to 0 for future compatibility

Figure 9-21.Timer Prescaler Load Register (TPLR)

Table 9-1.Timer Prescaler Load Register (TPLR) Bit Definitions

Bit Number	Bit Name	Reset Value			Description


23		0	Reserved. Write to zero for future compatibility.

22–21	PS[1–0]	0	Prescaler Source
			Control the source of the prescaler clock. The prescaler’s use of a TIO
			signal is not affected by the TCSR settings of the timer of the
			corresponding TIO signal. If the prescaler source clock is external, the
			prescaler counter is incremented by signal transitions on the TIO signal.
			The external clock is internally synchronized to the internal clock. The
			external clock frequency must be lower than the DSP56301 internal
			operating frequency divided by 4 (that is, CLK/4).
			NOTE: To ensure proper operation, change the PS[1–0] bits only when
			the prescaler counter is disabled. Disable the prescaler counter by
			clearing TCSR[TE] of each of three timers.

			PS1	PS0		Prescaler Clock Source

			0	0		Internal CLK/2

			0	1		TIO0

			1	0		TIO1

			1	1		TIO2

20–0	PL[20–0]	0	Prescaler Preload Value
			Contains the prescaler preload value, which is loaded into the prescaler
			counter when the counter value reaches 0 or the counter switches state
			from disabled to enabled. If PL[20–0] = N, then the prescaler counts N+1
			source clock cycles before generating a prescaler clock pulse. Therefore,
			the prescaler divide factor = (preload value) + 1.

Triple Timer Module

9-27

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Timer Prescaler Load Register Tplr, Prescaler Source, PS1 PS0

Models: DSP56301

9.4.2Timer Prescaler Load Register (TPLR)

Figure 9-21.Timer Prescaler Load Register (TPLR)

Table 9-1.Timer Prescaler Load Register (TPLR) Bit Definitions

Prescaler Source

PS1

PS0

Prescaler Preload Value

Triple Timer Module

DSP56301 specifications