Motorola DSP56301 Transmit 1 Enable, Transmit 2 Enable, Mode Select, Synchronous/Asynchronous

Models: DSP56301

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ESSI Programming Model

Table 7-4.ESSI Control Register B (CRB) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

 

Description

 

 

 

 

 

 

 

 

15

TE1

0

Transmit 1 Enable

 

 

 

Enables the transfer of data from TX1 to Transmit Shift Register 1. TE1 is

 

 

 

functional only when the ESSI is in Synchronous mode and is ignored

 

 

 

when the ESSI is in Asynchronous mode. When TE1 is set and a frame

 

 

 

sync is detected, transmitter 1 is enabled for that frame.

 

 

 

When TE1 is cleared, transmitter 1 is disabled after completing

 

 

 

transmission of data currently in the ESSI transmit shift register. Any data

 

 

 

present in TX1 is not transmitted. If TE1 is cleared, data can be written to

 

 

 

TX1; the TDE bit is cleared, but data is not transferred to transmit shift

 

 

 

register 1. If the TE1 bit is kept cleared until the start of the next frame, it

 

 

 

causes the SC0 signal to act as serial I/O flag from the start of the frame in

 

 

 

both Normal and Network mode. The transmit enable sequence in

 

 

 

On-Demand mode can be the same as in Normal mode, or the TE1 bit can

 

 

 

be left enabled.

 

 

 

Note:

The setting of the TE1 bit does not affect the generation of frame

 

 

 

 

sync or output flags.

 

 

 

 

14

TE2

0

Transmit 2 Enable

 

 

 

Enables the transfer of data from TX2 to Transmit Shift Register 2. TE2 is

 

 

 

functional only when the ESSI is in Synchronous mode and is ignored

 

 

 

when the ESSI is in Asynchronous mode. When TE2 is set and a frame

 

 

 

sync is detected, transmitter 2 is enabled for that frame.

 

 

 

When TE2 is cleared, transmitter 2 is disabled after completing

 

 

 

transmission of data currently in the ESSI transmit shift register. Any data

 

 

 

present in TX2 is not transmitted. If TE2 is cleared, data can be written to

 

 

 

TX2; the TDE bit is cleared, but data is not transferred to transmit shift

 

 

 

register 2. If the TE2 bit is kept cleared until the start of the next frame, it

 

 

 

causes the SC1 signal to act as a serial I/O flag from the start of the frame

 

 

 

in both Normal mode and Network mode. The transmit enable sequence

 

 

 

in On-Demand mode can be the same as in Normal mode, or the TE2 bit

 

 

 

can be left enabled.

 

 

 

Note:

The setting of the TE2 bit does not affect the generation of frame

 

 

 

 

sync or output flags.

 

 

 

 

13

MOD

0

Mode Select

 

 

 

Selects the operational mode of the ESSI, as in Figure 7-8 on page 7-26,

 

 

 

Figure 7-9 on page 7-27,and Figure 7-10 on page 7-27.When MOD is

 

 

 

cleared, the Normal mode is selected; when MOD is set, the Network

 

 

 

mode is selected. In Normal mode, the frame rate divider determines the

 

 

 

word transfer rate: one word is transferred per frame sync during the

 

 

 

frame sync time slot. In Network mode, a word can be transferred every

 

 

 

time slot. For details, see Section 7.3.

 

 

 

 

12

SYN

0

Synchronous/Asynchronous

 

 

 

Controls whether the receive and transmit functions of the ESSI occur

 

 

 

synchronously or asynchronously with respect to each other. (See Figure

 

 

 

7-7 on page 7-25.)When SYN is cleared, the ESSI is in Asynchronous

 

 

 

mode, and separate clock and frame sync signals are used for the

 

 

 

transmit and receive sections. When SYN is set, the ESSI is in

 

 

 

Synchronous mode, and the transmit and receive sections use common

 

 

 

clock and frame sync signals. Only in Synchronous mode can more than

 

 

 

one transmitter be enabled.

 

 

 

 

 

 

 

 

 

 

Enhanced Synchronous Serial Interface (ESSI)

7-21

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Motorola DSP56301 user manual Transmit 1 Enable, Transmit 2 Enable, Mode Select, Synchronous/Asynchronous

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.