Host Command Vector Register Hcvr | Motorola DSP56301 specification

Host-Side Programming Model

6.8.3Host Command Vector Register (HCVR)

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31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

HNMI

HV6	HV5	HV4	HV3	HV2	HV1	HV0	HC

UBM	UBM	UBM UBM UBM UBM UBM					UBM
PCI	PCI	PCI	PCI	PCI	PCI	PCI	PCI

Reserved. Read as zero. Write to zero for future compatibility. UBM = Universal Bus mode PCI = PCI mode

Figure 6-15.Host Command Vector Register (HCVR)

The HCVR is a 32-bit read/write register by which the host processor causes the DSP56300 core to execute a vectored interrupt. The host command feature is independent of any of the data transfer mechanisms in the HI32. It can cause any of the 128 possible interrupt routines in the DSP to be executed. The HCVR is written in accordance with the byte enables (HC3/HBE3-HC0/HBE0pins). Byte lanes that are not enabled are not written and the corresponding bits remain unchanged.

νWhen the HCVR is read to the PCI bus (DCTR[HM] = $1), the HAD[31– 0] pins are driven with the HCVR data during a read access; and these pins are written to the HCVR in a write access.

νIn a 24-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HTF] = $0 or HCTR[HRF] = $0), the HD[23– 0] pins are driven with the three least significant bytes of the HCVR in a read access; HD[23–0]are written to the three least significant bytes of the HCVR, the most significant portion is zero filled during the HCVR write.

νIn a 16-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HTF]≠$0 or HCTR[HRF]≠$0), the HD[15– 0] pins are driven with the two least significant bytes of

the HCVR in a read access; HD[15– 0] are written to the two least significant bytes of the HCVR, the most significant portion is zero filled during the HCVR write.

νIn PCI mode (DCTR[HM] = $1) memory space transactions, the HCVR is accessed if the PCI address is HI32_base_address: $018.

νIn a Universal Bus mode (DCTR[HM] = $2 or $3), the HCVR is accessed if the HA[10–3]value matches the HI32 base address (see Section 6.8.11, Memory Space Base Address Configuration Register (CBMA), on page 6-70)and the HA[2–0] value is $6.

Host Interface (HI32)

6-59

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Host Command Vector Register Hcvr

Models: DSP56301

Host-Side Programming Model

6.8.3Host Command Vector Register (HCVR)

PCI

Figure 6-15.Host Command Vector Register (HCVR)

Host Interface (HI32)

DSP56301 specifications