SCI Programming Model

8.6.1SCI Control Register (SCR)

The SCR is a read/write register that controls the serial interface operation. Seventeen of its 24 bits are defined.

.

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REIE

15

14

13

12

11

10

9

8

 

 

 

 

 

 

 

 

SCKP

STIR

TMIE

TIE

RIE

ILIE

TE

RE

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

WOMS

RWU

WAKE

SBK

SSFTD

WDS2

WDS1

WDS0

 

 

 

 

 

 

 

 

—Reserved bit; read as 0; write to 0 for future compatibility.

Figure 8-3.SCI Control Register (SCR)

Table 8-2.SCI Control Register (SCR) Bit Definitions

Bit

Bit Name

Reset

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23–17

 

0

Reserved. Write to 0 for future compatibility.

 

 

 

 

 

 

16

REIE

0

Receive with Exception Interrupt Enable

 

 

 

Enables/disables the SCI receive data with exception interrupt. If REIE is cleared, the

 

 

 

receive data with exception interrupt is disabled. If both REIE and RDRF are set, and

 

 

 

PE, FE, and OR are not all cleared, the SCI requests an SCI receive data with

 

 

 

exception interrupt from the interrupt controller. Either a hardware RESET signal or a

 

 

 

software RESET instruction clears REIE.

 

 

 

 

15

SCKP

0

SCI Clock Polarity

 

 

 

Controls the clock polarity sourced or received on the clock signal (SCLK), eliminating

 

 

 

the need for an external inverter. When SCKP is cleared, the clock polarity is positive;

 

 

 

when SCKP is set, the clock polarity is negative. In Synchronous mode, positive

 

 

 

polarity means that the clock is normally positive and transitions negative during valid

 

 

 

data. Negative polarity means that the clock is normally negative and transitions

 

 

 

positive during valid data. In Asynchronous mode, positive polarity means that the

 

 

 

rising edge of the clock occurs in the center of the period that data is valid. Negative

 

 

 

polarity means that the falling edge of the clock occurs during the center of the period

 

 

 

that data is valid. Either a hardware RESET signal or a software RESET instruction

 

 

 

clears SCKP.

 

 

 

 

14

STIR

0

Timer Interrupt Rate

 

 

 

Controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is cleared, the

 

 

 

divide-by-32 is inserted in the chain. When STIR is set, the divide-by-32 is bypassed,

 

 

 

thereby increasing timer resolution by a factor of 32. Either a hardware

RESET

signal

 

 

 

or a software RESET instruction clears this bit. To ensure proper operation of the timer,

 

 

 

STIR must not be changed during timer operation (that is, if TMIE = 1).

 

 

 

 

 

 

8-12

DSP56301 User’s Manual

Page 248
Image 248
Motorola DSP56301 user manual SCI Control Register SCR, Reie, Stir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.