Motorola DSP56301 user manual DSP56300 Core Features

DSP56300 Core Features

1.3DSP56300 Core Features

All DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements, such as memories and peripherals. New modules can be added to the library to meet customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. In particular, the DSP56301 includes Motorola’s JTAG port and OnCE ™ module. Core features are fully described in the DSP56300 Family Manual. This manual, in contrast, documents pinout, memory, and peripheral features. Core features are as follows:

ν80/100 Million Instructions per Second (MIPS) using an internal 80/100 MHz clock at 3.0–3.6 V, depending on the revision of the DSP56301

ν

ν

ν

ν

ν

Object code compatible with the DSP56000 core

Highly parallel instruction set

Data Arithmetic Logic Unit (Data ALU)

—Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)

—56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)

—Conditional ALU instructions

—24-bit or 16-bit arithmetic support under software control

Program Control Unit (PCU)

—Position Independent Code (PIC) support

—Addressing modes optimized for DSP applications (including immediate offsets)

—On-chip instruction cache controller

—On-chip memory-expandable hardware stack

—Nested hardware DO loops

—Fast auto-return interrupts

Direct Memory Access (DMA) Controller

—Six DMA channels supporting internal and external accesses

—One-, two-, and three- dimensional transfers (including circular buffering)

—End-of-block-transfer interrupts

—Triggering from interrupt lines and all peripherals

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