Triple Timer IPL, Host IPL | Motorola DSP56301 specs

Programming Sheets

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Sheet 2 of 2

Interrupt Priority

		Triple Timer IPL

	TOL1			TOL0			Enabled		IPL

	0			0			No		—
	0			1			Yes		0
	1			0			Yes		1
	1			1			Yes		2
																					ESSI1 IPL

																		S1L1		S1L0				Enabled					IPL
									SCI IPL								0			0						No			—
									SCI IPL								0			1						Yes			0
							SCL1		SCL0		Enabled		IPL				1			0						Yes			1
							0	0				No	—				1			1						Yes			2
							0	1			Yes		0
							0	1			Yes		0
							1	0			Yes		1
							1	1			Yes		2
							1	1			Yes		2
																											ESSI0 IPL

																							S0L1				S0L0		Enabled						IPL
																						0					0			No					—
																						0					1			Yes				0
																						1					0			Yes				1
																						1					1			Yes				2



																														Host IPL

																											HPL1		HPL0				Enabled			IPL

																											0		0						No		—
																											0		1					Yes		0
																											1		0					Yes		1
																											1		1					Yes		2

23	22	21		20		19	18	17		16	15	14	13		12		11	10	9	8		7	6	5	4		3	2	1	0
23	22	21		20		19	18	17		16	15	14	13		12		11	10	9	8		7	6	5	4		3	2	1	0
*0	*0		*0	*0	*0		*0		*0	*0	*0	*0		*0	*0		*0	*0	TOL1	TOL0		SCL1	SCL0	S1L1	S1L0		S0L1	S0L0	HPL1	HPL0
		$0						$0					$0

Interrupt Priority Register (IPRP)														X:$FFFFFE Read/Write
Reset = $000000

* = Reserved, Program as 0

Figure B-4.Interrupt Priority Register Peripherals (IPRP)

B-16	DSP56301 User’s Manual

Image 328

Motorola DSP56301 user manual Triple Timer IPL, Host IPL, Interrupt Priority Register Iprp $FFFFFE Read/Write

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Contents

DSP56301 User’s Manual Revision 3, March How to reach us USA/EUROPEJapan ASIA/PACIFICPage Page Contents Chapter Memory Configuration Chapter Core Configuration Chapter Programming the Peripherals Chapter Host Interface HI32 Chapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Chapter a Bootstrap Program Chapter B Programming Reference Chapter Triple Timer ModuleIndex Figures DSP56301 User’s Manual Xii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables Tables Essi Clock Sources Manual Organization Overview High True/Low True Signal Conventions Signal/Symbol Logic State Signal State VoltageManual Conventions Ground2 Ground PIN is a generic term for any pin on the chip DSP56300 Core Features CE = MS = Program RAM Instruction Data RAM Switch Size Cache SizeSize Cache DSP56300 Core Functional Blocks Data ALU Data ALU Registers Address Generation Unit AGUMultiplier-Accumulator MAC Program Control Unit PCU PLL and Clock Oscillator Jtag TAP and OnCE Module Internal Buses DSP56301 Switch Memory ConfigurationOn-Chip Memory Memory Expansion Area DMAExpansion Area General-Purpose Input/Output Gpio signals PeripheralsHost Interface HI32 Enhance Synchronous Serial Interface Essi Triple Timer Module Serial Communications Interface SCI Related Documents and Web Sites DSP56301 DocumentationName Description Order Number DSP56300FM/AD DSP56301 Functional Signal Groupings Timers JTAG/OnCE PortEnhanced Synchronous Serial Interfaces ESSI0 ESSI1 DSP56301 See -2for a listing of the Host Interface/Port B SignalsPort a Host Interface/Port B Detail Signal Diagram Power Power InputsGround Signals Ground Clock Signals Phase-Lock Loop SignalsClock PLL External Memory Expansion Port Port a External Address BusExternal Data Bus External Bus Control Signals are tri-stated Arbitration is reset to the bus slave stateOutput Tri-stated Is an active-low output that is Output Tri-stated Is asserted for half a clock CAS Bclk Interrupt and Mode Control Interrupt and Mode ControlSignal State Type During Signal Description Name Nonmaskable Interrupt-After Host Interface HI32 10.Host Interface Command 0-3/Byte Enable 0-3 -When the HI32 is programmed HBS HparHdak Hperr Hserr HirqHstop HWR 11.Summary of HI32 Signals and Modes Signal PCI Mode Enhanced Universal Bus Mode Gpio Mode Name HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9 HAD10 HD2 HIO10HAD11 HD3 HIO11 HAD12 HD4 HIO12 PCI 12.Host Port Pins HI32Gpio Bus Command/Byte Enable Host Address Bus Host Target Ready Host Data Bus EnableReserved Host Initiator Ready Host Data Bus Direction Parity Error DMA Request Bus Grant Host Address EnableHost Device Select Host Select Acknowledge Host Lock Bus Strobe Host System Error Host Interrupt Request Bus Request Host Transfer AcknowledgeHreq is deasserted in the same PCI Hstr Hstop HWR/HRW Host Stop Host Write/Read-WriteHRD/HDS Initialization Device Select Host Read/Data Strobe Host Bus Clock Address/Data Multiplexed Bus Data Bus Hardware Reset Enhanced Synchronous Serial InterfaceHost Interrupt a Active low, open drain output pin 13.Enhanced Synchronous Serial Interface PC0PC1 PC2 SCK0 PC3SRD0 PC4 14.Enhanced Serial Synchronous Interface PD0PD1 PD2 SCK1 PD3SRD1 PD4 Serial Communications Interface SCI Timers15.Serial Communication Interface 16.Triple Timer Signals Timer 0 Schmitt-Trigger Input/Output- When TimerTimer 1 Schmitt-Trigger Input/Output- When Timer Timer 2 Schmitt-Trigger Input/Output- When timer Jtag and OnCE Interface Signal Name Type State During Signal Description Reset17.JTAG/OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Memory Configuration Program Memory Space Internal Program Memory Memory Switch Modes-Program MemoryInstruction Cache Program Bootstrap ROM Memory Switch Modes-X Data MemoryMemory Configuration Data Memory Space Internal I/O Space-X Data Memory Memory Switch Modes-Y Data MemoryInternal Y Data Memory Dynamic Memory Configuration Switching External I/O Space-Y Data Memory Sixteen-Bit Compatibility Mode Configuration Internal Memory Configuration SummaryDSP56301 RAM Configurations DSP56301 RAM Address Ranges by Configuration Memory Maps DefaultRAM 16-Bit Space With Default RAM 0, 0 None 64K $000-$FFF $000-$7FF 16M $000-$800 $000-$BFF 16-Bit Space With Switched Program RAM 0, 1 None 64K $000-$7FF $000-$BFF Instruction Cache Enabled 1, 0 $000-$BFF $000-$7FF Not addressable 16-Bit Space With Instruction Cache Enabled 1, 0 Addressable $000-$3FF $000-$BFF Not addressable $0400 $0000 Core Configuration Core Configuration Reset Description Vector Operating ModesDSP56301 Operating Modes Mode Operating Mode Definitions Mode Description Low. The DSP56301 is written with 24-bit-wide words Address attributes selected defaultDSP Clkout rate must be 5/3 of the PCI clock Bootstrap Program Central Processor Unit CPU Registers Status Register SR DMA OMR Cache Enable Sixteen-Bit Arithmetic ModeDo Forever Flag Do Loop Flag Sixteen-Bit Compatibility Mode Scaling Mode Scaling Rounding Bit SEquation ModeInterrupt Mask Priority Exceptions Exceptions Masked Permitted Bit Number Bit Name Reset Value Description Limit Scaling Mode Integer PortionExtension Unnormalized Operating Mode Register OMR Operating Mode Register OMR Bit DefinitionsStack Extension Enable Stack Extension Wrap Flag Address Trace Enable Address Attribute Priority DisableAsynchronous Bus Arbitration Enable Stack Extension Overflow Flag Cache Burst Mode Enable Memory Switch ModeBus Release Timing Synchronize Select Configuring Interrupts Bit Number Bit Name Reset Value Description Stop Delay ModeExternal Bus Disable Chip Operating Mode Interrupt Priority Registers Iprc and Iprp Interrupt Priority Level Bits Interrupt Table Memory MapInterrupt Sources VBA$1A VBA$1CVBA$1E VBA$2A Interrupt Source Priorities Within an IPL Processing Interrupt Source Priorities Within an IPLPriority Interrupt Source Host command interrupt TIMER0 overflow interruptTIMER0 compare interrupt TIMER1 overflow interrupt PLL Control Register Pctl PLL Control Register Pctl Bit Definitions Bus Interface Unit BIU Registers Bus Control Register Bus Default Area Wait State Control Bus Area 3 Wait State ControlBus Area 2 Wait State Control Bus Area 1 Wait State Control Dram Control Register DCR BRP BRF7 BRF6BRF3 BRF2 BRF1 Bstr Bren BME Bple BPS1 10.DRAM Control Register DCR Bit Definitions Bus Page Logic Enable Bus Dram Page SizeBus Row Out-of-page Wait States Bus Column In-Page Wait State Bus Address to Compare Address Attribute Registers AAR0-3Bus Number of Address Bits to Compare Bus Packing Enable Bus Y Data Memory EnableBus X Data Memory Enable Bus Program Memory Enable DMA Control Registers 5-0 DCR5-0 DIE DTM2 DTM1 DTM0Dcon DAM5 DAM4 DAM3 DAM2 DAM1 DAM0 DMA Interrupt Enable DMA Transfer ModeDTM2-0 Trigger Cleared Transfer Mode After 12.DMA Control Register DCR Bit Definitions Number Value DMA Channel PriorityDMA address generation logic, buses, and so forth DPR1-0 Channel Priority OMR CDP1-0 CP1-0 Core Priority DMA Continuous Mode EnableDcon DMA Request Source Three-Dimensional ModeDRS4-0 Requesting Device DDS1 DDS0 Device Identification Register IDRDSS1 DSS0 Jtag Identification ID Register Jtag Boundary Scan Register BSRVersion Information Design Center Number Identity See Note Jtag Boundary Scan Register BSR DSP56301 User’s Manual Peripheral Initialization Steps Programming the Peripherals Mapping the Control Registers Data Transfer MethodsPolling Data Memory Interrupts 3 DMA General-Purpose Input/Output GpioAdvantages and Disadvantages Port B Signals and Registers Port D Signals and Registers Port C Signals and RegistersPort E Signals and Registers Triple Timer Signals and Registers Timer Gpio General-Purpose Input/Output Gpio DSP56301 User’s Manual Features Host Interface HI32 HI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview PCI Configuration Space DSP-Side RegistersDSP DMA Data Bus DSP Global Data Bus Data transfer format converter Data Transfer Paths Host-to-DSP Data Path DSP-To-Host Data Path HI32 PCI Master Data Transfer Formats DpmcFC1 FC0 Two least significant bytes of two Hrxm Hctr Transmit Data Transfer FormatHTF1 HTF0 Receive Transfer Data Formats DSP to Host Data Transfer FormatHRF Three least significant Hrxs bytes Receive Transfer Data Formats Reset States Type Entered when DescriptionDSP-Side Operating Modes HRST/HRST Terminate and Reset Dctrhm = $0 PCI Mode Dctrhm = $1HI32 Mode PCI Example 6-1. PCI /DMA Throughput 32-Bit Multfactor Gpio Mode Dctrhm = $4 Self-Configuration Mode Dctrhm = $5 Example 6-3. Self-Configuration Procedure for PCI Mode PCI Bus Universal Bus Mode Host Port PinsHost Port Pin Functionality DSP56301 ISA Master Slave HI32 DSP-Side Programming Model Memory Register Address ModeHI32 Programming Model, DSP Side DSP Control Register Dctr Mode Description ValueBit Number Bit Name 10.DSP Control Register Dctr Bit Definitions Host Data Strobe Mode HtapHost Transfer Acknowledge Polarity Host Read/Write Polarity Slave Receive Interrupt Enable Slave Transmit Interrupt EnableHost Command Interrupt Enable DSP PCI Control Register Dpcr Insert Address Enable Receive Buffer Lock Enable11.DSP PCI Control Register Dpcr Bit Definitions IAE Master Wait State Disable Master Access Counter EnableForce Hserr Transfer Complete Interrupt Enable Transaction Termination Interrupt EnableTransaction Abort Interrupt Enable Parity Error Interrupt Enable BL4 DSP PCI Master Control Register DpmcBL1 BL0 12.DSP PCI Master Control Register Dmpc Bit Definitions Data Transfer Format ControlA PCI DSP-to-Host transaction A PCI Host-to-DSP transaction PCI Data Burst Length DSP PCI Transaction Address High DSP PCI Address Register Dpar 13.DSP PCI Address Register Dpar Bit DefinitionsBE2 BE1 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 PCI Bus Command C3-0 Command TypeDSP PCI Transaction Address Low AR1 AR0 Bit Bit Name Reset Mode Description Number Value DSP Status Register DSR14.DSP Status Register DSR Bit Definitions 2322212019181716 Srrq UBM Slave Receive Data Request Mode Description Number Value Host Command Pending14. DSP Status Register DSR Bit Definitions Slave Transmit Data Request DSP PCI Status Register Dpsr 15.DSP PCI Status Register Dpsr Bit DefinitionsRdcq MDT Hdtc Trty Tdis TAB MAB Aper Marq Mrrq Mtrq MWS Master Data Transferred PCI Host Data Transfer CompletePCI Time Out Termination PCI Target Retry PCI Data Parity Error PCI Address Parity ErrorPCI Target Disconnect PCI Target Abort DSP Receive Data Fifo Drxr 15. DSP PCI Status Register Dpsr Bit DefinitionsPCI Master Wait States PCI Master Receive Data Request DSP Master Transmit Data Register Dtxm DSP Slave Transmit Data Register Dtxs DSP Host Port Gpio Data Register Dath DSP Host Port Gpio Direction Register Dirh16.DATH and Dirh Functionality 17.HI32 Programming Model, Host-Side Registers Host-Side Programming ModelMemory Register Host-Side Programming Model 18.PCI Bus Commands Executed as Command TypeHC3/HBE3-HC0/HBE0 Ignored 21. Host-Side Registers Universal Bus Mode Address Space 20. Host-Side Registers PCI Configuration Address Space19. Host-Side Registers PCI Memory Address Space 1 HI32 Control Register Hctr 13.Host Interface Control Register Hctr Bit Bit Name Reset Mode Description Number Target Wait State Disable22.Host Interface Control Register Hctr Bit Definitions Twsd PCI Host Receive Data Transfer Format Host Transmit Data Transfer Format SFT UBM Inserted AddressSlave Fetch Type Universal Bus mode Fetch SFT = Cleared when the DSP56300 core writes toReset, and Strq and Hstrhrrq are cleared Data path is lost when the reset state is Dmae Haen Dmae UBMHirq Receive Req uest Enable Rreq UBMDmae Treq Rreq Hirq Pin Hdrq pin Host Interface Status Register Hstr Hreq Hint HF5 HF4 HF3Trdy UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCI 23.Host Interface Status Register Hstr Bit Definitions Host RequestHost interrupt a Treq Rreq Hreq Host Transmit Data Request Host Receive Data RequestTransmitter Ready Host Command Vector Register Hcvr 15.Host Command Vector Register Hcvr 24.Host Command Vector Register Hcvr Bit Definitions Host Command VectorBit Bit Name Reset Value Mode Description Number Hnmi UBM Host Command When the DSP56300 core acknowledges the host commandHost Master Receive Data Register Hrxm Host Slave Receive Data Register Hrxs Host Transmit Data Register Htxr PCI Mode Dctrhm = $1 Universal Bus mode Dctrhm = $2 or $3 Device ID/Vendor ID Configuration Register CDID/CVID Status/Command Configuration Register CSTR/CCMRDPE SSE RMA RTA STA DPR Fbbc Detected Parity Error Signaled System ErrorSignalled Target Abort Received Master Abort System Error Enable Wait Cycle Control hardwired to zeroParity Error Response Bus Master Enable Class Code/Revision ID Configuration Register CCCR/CRID Header Type hardwired to $00 HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0HT7-0 Read-only bits that identify the layout of bytes $10-$3F Cache Line Size Latency Timer HighCcls Memory Space Base Address Configuration Register Cbma Universal Bus Mode Base AddressPM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Base Address High/Low 29. Memory Space Base Address Configuration Register Cbma Memory Base Address Low Hardwired to zerosPre-Fetch Hardwired to zero Memory Space Hardwired to zeros Example 6-5. Code for Setting the Csid Interrupt Line-Interrupt Pin Configuration RegisterCILP IL5 IL4IL1 IL0 Maxlat HI32 Programming Model/Quick Reference HS PH PSDctr Hcie UBM Hrsp Clrt Dpcr MtieRble Dpmc DparDSR HCP Hact Dpsr Aper DperHdtc Rdcq Treq DmaeISA/EISA SFT Hcvr HnmiHrxm Hrxs Ccmr RMA CccrChty Cbma MSI GDB DDB Rclk Rsma Rsmb Tsma Tclk STDTsmb TX0 CRA SC0 Essi Enhancements Essi Data and Control Signals Serial Transmit Data Signal STDSerial Receive Data Signal SRD Serial Clock SCK Serial Control Signal SC0 Serial Control Signal SC1 Control Bits Essi Signals Mode and Signal DefinitionsSYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Serial Control Signal SC2 Essi After ResetOperation Initialization Exceptions Operation Write data to all enabled transmit registers Normal/Network/On-Demand Mode Selection Operating Modes Normal, Network, and On-Demand Synchronous/Asynchronous Operating Modes Frame Sync Signal FormatFrame Sync Selection Word Length Frame Sync and Data Word Timing Frame Sync Length for Multiple DevicesFrame Sync Polarity Byte Format LSB/MSB for the Transmitter Flags Essi Programming Model Essi Control Register a CRAWL2 WL1 WL0 ALC PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Essi Control Register a CRA Bit Definitions Select SC1Word Length Control Essi Word Length Selection Alignment Control Frame Rate Divider ControlPrescaler Range Prescale Modulus Select CRBTE1 CRBOF0 SSISRIF0 Crbsyn =Rclock Tclock Essi Control Register B CRB ShfdOF1 OF0 ESSI0 X$FFFFB6, ESSI1 X$FFFFA6 Essi Control Register B CRB Bit Definitions Transmit Interrupt Enable Receive EnableTransmit 0 Enable TIE Transmit 1 Enable Transmit 2 EnableMode Select Synchronous/Asynchronous FSL1 FSL0 Serial Control Direction OF1Serial Output Flag OF0 Serial Clock RX Frame Sync RX Serial Data Serial Clock RX, TX Frame Sync RX, TX Serial DataTX Frame Sync TX Serial Data CRB SYN Bit Operation Essi Bit SSI Control Register B CRB READ/WRITE Bit OperationReceiver Interrupt or DMA Request and Flags Set Frame Sync FSL0 = 0, FSL1 = Data Out Flags Frame Sync FSL0 = 0, FSL1 = Data Flags Receiver Overrun Error Flag Transmitter Underrun Error FlagEssi Status Register Ssisr Receive Data Register Full Essi Receive Shift Register Receive Frame Sync FlagTransmit Frame Sync Flag Serial Input Flag Essi Receive Data Register RX Essi Transmit Shift Registers Receive Registers Transmit Registers Transmit Middle Byte Transmit Low Byte Register 24 Bit WL0Least Significant MSB Essi Transmit Data Registers TX2-0 Essi Time Slot Register TSRTransmit Slot Mask Registers TSMA, Tsmb TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 15.ESSI Transmit Slot Mask Register B Tsmb Receive Slot Mask Registers RSMA, Rsmb RS7 RS6RS1 RS0 RS15 RS14 RS13 RS12 RS11 RS10 Gpio Signals and Registers Port Control Registers Pcrc and Pcrd Port Direction Registers Prrc and Prrd Essi Port Signal ConfigurationsESSI0/ESSI1 Port Data Registers Pdrc and Pdrd 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFAD Serial Communication Interface SCI Serial Communication Interface SCI Asynchronous Mode Synchronous ModeMultidrop Mode I/O Signals Wired-OR ModeAddress Mode Wakeup Transmitting Data and Address Characters Transmit Data TXD Receive Data RXDSCI Serial Clock Sclk SCI After Reset SCI Registers After ResetReie Sckp Stir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd SCI Initialization Preamble, Break, and Data Transmission Priority Bootstrap Loading Through the SCI Boot Mode 2 or a Exceptions SCI Programming Model Bit Synchronous Data Shift Register Mode WDS2 WDS1 WDS0Bit Asynchronous 1 Start, 8 Data, 1 Stop Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 Stop SCI Data Word Formats Ssftd = 0 Reie SCI Control Register SCRStir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 Timer Interrupt Enable SCI Transmit Interrupt EnableSCI Receive Interrupt Enable Idle Line Interrupt Enable Wired-OR Mode Select Receiver EnableWoms Receiver Wakeup Enable Wakeup Mode SelectSend Break SCI Shift Direction Word Select Mode Word FormatsWDS1 WDS0 SCI Status Register SCI Status Register SSR Bit Definitions SCI Status Register SSRIdle Rdrf Tdre Trne Tdre Idle Line FlagTransmitter Empty SCI Clock Control Register Sccr TCM RCM SCP CODTCM RCM Sclk Bit Counter Divide byCD11-0 Sckp = 0 + Sckp = RX, TX Data Ssftd = X1 Clock X16 Clock Sckp = SCI Receive Register SRX SCI Data RegistersSCI Receive Data Shift Register SCI Transmit Register STX PE2 PE1 PE0 Port E Control Register PcreSclk TXD RXD Port E Direction Register Prre Port E Data Register PdrePRRE1 PRRE0 PDRE1 PDRE0 Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer Module Triple Timer Module Block Diagram Individual Timer Block DiagramGDB Tpcr Timer After Reset Timer Module Block Diagram Timer Initialization Timer Exceptions TCSR0 Tcie Triple Timer Modes Timer Gpio ModeTC3 TC2 TC1 TC0 TIO TLR Mode 0 internal clock, no timer output TRM =TCR Tcpr Mode 1 internal clock TRM = Timer Pulse ModeOutput Pulse width = timer clock Period Timer Toggle Mode Mode 2 internal clock TRM = 1 first eventToggle Timer = write preload = write compare Clock CLK/2 or prescale CLK = write preload Mode 2 internal clock TRM == write compare Clock CLK/2 or prescale CLK Timer Event Counter Mode Mode 3 internal clock TRM =Input External TIO Cpuclk + 10.Event Counter Mode, TRM = = write compare Clock Signal Measurement Modes Measurement Input Width ModeInput Input width Measurement Mode 4 internal clock TRM = Mode 4 internal clock TRM = 1 first event Measurement Input Period Mode Mode 5 internal clock TRM =First event = write preload = write compare Input period Measurement Internal May occur TOF=1 Counting, doesReads TCR period Measurement Capture Mode Mode 6 internal clock TRM =Interrupt Service reads TCR delay = M N clock periods Internal PWM Pulse Width Modulation PWM, ModePulse width modulation Mode 7 internal clock TRM = 16.Pulse Width Modulation Toggle Mode, TRM = 17.Pulse Width Modulation Toggle Mode, TRM = Watchdog Pulse Mode Watchdog ModesPulse Watchdog Output Internal Software does not reset watchdog timer watchdog times out Mode 9 internal clock TRM == write preload First event Watchdog Toggle Mode Mode 10 internal clock TRM =Watchdog Output Toggle Triple Timer Module Programming Model Special CasesDMA Trigger Prescaler Counter Timer Prescaler Load Register Tplr23 22 21 20 19 18 17 Tplr = $FFFF83 Timer Prescaler Load Register Tplr Prescaler SourcePS1 PS0 Prescaler Preload Value Timer Prescaler Count Register Tpcr Timer Control/Status Register TcsrTCF TOF PCE TRM INV Timer Compare Flag Timer Overflow FlagPrescaler Clock Enable Data Output Direction Timer Reload ModeInverter Timer Control Number Function Timer Compare Interrupt Enable Timer Overflow Interrupt EnableTimer Enable TIO Programmed as Input TIO Programmed as Output Mode INV = Pulse generated by Timer has Timer has negative Timer Load Register TLRPositive polarity Timer Compare Register Tcpr Timer Count Register TCR Appendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Chapter B Programming Reference Table B-1.Guide to Programming Sheets Table B-2. Internal I/O Memory Map X Data Memory Internal I/O Memory MapBit Address Register Name Table B-2.Internal I/O Memory Map X Data Memory Peripheral Bit Address Register Name $FFCD $FFFFCD $FFCC $FFFFCC$FFCB $FFFFCB $FFCA $FFFFCA Essi $FFBC $FFFFBC $FFBB $FFFFBB$FFBA $FFFFBA $FFB9 $FFFFB9 Essi $FFAC $FFFFAC $FFAB $FFFFAB$FFAA $FFFFAA $FFA9 $FFFFA9 $FFFF92 $FFFF91$FFFF90 $FF8F $FFFF8F Interrupt Sources and Priorities Table B-3. Interrupt Sources Table B-3.Interrupt Sources VBA$6AVBA$6C VBA$6E Nonmaskable Host Command Interrupt Table B-4.Interrupt Source Priorities Within an IPL ESSI0 receive last slot interrupt Programming Sheets Figure B-1.Status Register SR External Bus Disable Stop DelayMemory Switch Mode Burst Mode Enable Irqd Mode Irqc ModeIrqb Mode Irqa Mode Host IPL Triple Timer IPLInterrupt Priority Register Iprp $FFFFFE Read/Write PLL Control Register Pctl $FFFFFD Read/Write Crystal Range Bit Xtlr Default Area Wait Control, Bits Bus Control Register BCR $FFFFFB Read/WriteBus Request Hold, Bit Bus Lock Hold, Bit Dram Control Register DCR $FFFFFA Read/Write Bus Packing Enable, Bit Bus Y Data Memory Enable, BitBus X Data Memory Enable, Bit Bus Program Memory Enable, Bit Reset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/Write DMA Control Registers DCR5-DCR0 DSP Control Register Dctr Read/Write Address X FFFFC5 Application = Enables master receive interrupts DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write Figure B-12.DSP PCI Master Control Register Dpmc PCI Bus Command, Bits Figure B-13.DSP PCI Address Register Dpar HI32 Control Register Hctr Read/Write HI32 Command Vector Register Hcvr Read/Write Host Non-Maskable Interrupt, Bit Detected Parity Error, Bit Signaled System Error, BitSignalled Target Abort, Bit System Error Enable, Bit Latency Timer High, Bits Read/WriteHeader Type, Bits Cache Line Size, Bits HI32 Memory Space Base Address Configuration Register Cbma Reset = $00000000PCI Mode Base Address High, Bits Pre-fetch, Bit Memory Space Indicator, Bit Subsystem ID Register, Bits 31-16 Specifies the subsystem ID Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/Write ESSI1-X$FFFFA5 Read/Write ESSI0-X$FFFFB6 Read/Write Essi Control Register B CRBxESSI1-X$FFFFA6 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/Write ESSI1-X$FFFFA4 Read/WriteEssi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write ESSI1-X$FFFFA3 Read/Write SCI Control Register SCR $FFFF9C Read/Write Receiver Clock Mode/Source SCI Clock Control Register Sccr Address X$FFFF9B Read/WriteClock Out Divider Figure B-25.Timer Prescaler Load Register Tplr Timer Prescaler Load Register Tplr $FFFF83 Read/Write Timer Control/Status Register TCSR0$FFFF8F Read/Write TCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write Timer Load Register TLR0-2 TLR0-X$FFFF8E Write Only TLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write Only Host Data Direction Register Hddr X$FFFFC8 Write Port B HI08Host Data Register HDR $FFFFC9 Write Port C ESSI0 Port C Control Register Pcrc $FFFFBF Read/WritePort C Direction Register Prrc $FFFFBE Read/Write Port C Gpio Data Register Pdrc $FFFFBD Read/Write Port D ESSI1 Port D Control Register Pcrd $FFFFAF Read/WritePort D Direction Register Prrd $FFFFAE Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/Write Port E SCI Port E Control Register Pcre $FFFF9F Read/WritePort E Direction Register Prre $FFFF9E Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/Write Programming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual