Reset States

6.4Reset States

Table 6-6describes the various HI32 reset states.

Table 6-6. HI32 Reset

 

Type

 

Entered when

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

Hardware

HS

The DSP56300 core

These resets force the HI32 DSP side state machines, control

 

Reset

 

RESET pin is asserted.

registers, and status registers to their initial states. These resets also

 

 

 

 

 

 

activate the Personal Software (PS) reset.

 

Software

 

The RESET instruction

 

 

 

 

Reset

 

is executed.

 

 

 

 

 

 

 

Personal

PS

The DSP56300 core

The HI32 terminates the current PCI transaction (if it is an active PCI

 

Software

 

writes zeros to the HI32

agent), clears the HACT bit in the DSP Status Register (DSR) and

Core

Reset

 

mode bits HM[2–0] in

enters the personal software (PS) reset state. All data paths are

 

 

the DSP control register

cleared. In the personal software reset state, the HI32 is a PCI agent

 

 

 

DSP56300

 

 

or the HS reset has

and responds to all memory and configuration space transactions

 

 

executed.

with a retry event. If connected to other buses (for example, ISA bus,

 

 

 

 

 

 

 

 

 

DSP56300 core-based DSP Port A bus, and so on) all outputs are

 

 

 

 

 

 

high impedance.

 

 

 

 

 

the

STOP mode

ST

The STOP instruction

This reset forces all host port pins to the disconnected state: all

 

 

executes.

outputs are high impedance, all inputs are electrically disconnected.

by

 

 

 

 

 

 

 

The host port pins are affected immediately.

Initiated

 

 

 

 

 

Status Register (DSR) is zero.

 

 

 

 

 

 

Note: This mode can execute only when the HACT bit in the DSP

 

 

 

 

 

 

Personal

PH

The HI32

 

 

This reset forces the HI32 host-side state machines, control

Host

HRST/HRST

Hardware

 

pin is asserted.

registers, and configuration registers to their initial states. All host

the

Reset

 

 

 

 

port pins, except HRST/HRST, are forced to the disconnected state:

 

 

 

 

 

by

 

 

 

 

 

all outputs are high impedance, all inputs are electrically

 

 

 

 

 

disconnected. The DSP-side state machines are not affected.

Initiated

 

 

 

 

 

 

 

 

 

 

The HRST/HRST pin is ignored in Self-Configuration mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

6.5DSP-Side Operating Modes

The HI32 Mode (DCTR[HM]) bits in the DSP Control Register (DCTR) control the HI32 operating modes (see Table 6-10,DSP Control Register (DCTR) Bit Definitions, on

page 6-23). The DSP56300 core can change the value of the DCTR[HM] bits only when the HI32 is in the personal software reset state (DCTR[HM] = $0, DSR[HACT] = 0). These bits must not be changed together (that is, in the same core write) with any of the following bits: HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, or HIRD. The combinations DCTR[HM] = $6, DCTR[HM] = $7 are reserved for future expansion and should not be used.

6-12

DSP56301 User’s Manual

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Motorola DSP56301 user manual Reset States, DSP-Side Operating Modes, Type Entered when Description, Hrst/Hrst
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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