Motorola DSP56301 Reset States, DSP-Side Operating Modes, Type Entered when Description

Reset States

6.4Reset States

Table 6-6describes the various HI32 reset states.

Table 6-6. HI32 Reset

	Type		Entered when		Description
	Hardware	HS	The DSP56300 core		These resets force the HI32 DSP side state machines, control
	Reset		RESET pin is asserted.		registers, and status registers to their initial states. These resets also
					activate the Personal Software (PS) reset.
	Software		The RESET instruction
	Reset		is executed.
	Personal	PS	The DSP56300 core		The HI32 terminates the current PCI transaction (if it is an active PCI
	Software		writes zeros to the HI32		agent), clears the HACT bit in the DSP Status Register (DSR) and
Core	Reset		mode bits HM[2–0] in		enters the personal software (PS) reset state. All data paths are
			the DSP control register		cleared. In the personal software reset state, the HI32 is a PCI agent
DSP56300			or the HS reset has		and responds to all memory and configuration space transactions
			executed.		with a retry event. If connected to other buses (for example, ISA bus,
					DSP56300 core-based DSP Port A bus, and so on) all outputs are
					high impedance.
the	STOP mode	ST	The STOP instruction		This reset forces all host port pins to the disconnected state: all
			executes.		outputs are high impedance, all inputs are electrically disconnected.
by
					The host port pins are affected immediately.
Initiated					Status Register (DSR) is zero.
					Note: This mode can execute only when the HACT bit in the DSP
	Personal	PH	The HI32		This reset forces the HI32 host-side state machines, control
Host				HRST/HRST
	Hardware		pin is asserted.		registers, and configuration registers to their initial states. All host
the	Reset				port pins, except HRST/HRST, are forced to the disconnected state:
by					all outputs are high impedance, all inputs are electrically
					disconnected. The DSP-side state machines are not affected.
Initiated
					The HRST/HRST pin is ignored in Self-Configuration mode.

6.5DSP-Side Operating Modes

The HI32 Mode (DCTR[HM]) bits in the DSP Control Register (DCTR) control the HI32 operating modes (see Table 6-10,DSP Control Register (DCTR) Bit Definitions, on

page 6-23). The DSP56300 core can change the value of the DCTR[HM] bits only when the HI32 is in the personal software reset state (DCTR[HM] = $0, DSR[HACT] = 0). These bits must not be changed together (that is, in the same core write) with any of the following bits: HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, or HIRD. The combinations DCTR[HM] = $6, DCTR[HM] = $7 are reserved for future expansion and should not be used.

6-12 DSP56301 User’s Manual