network enhancements 7-2

Time Slot Register (TSR) 7-8,7-33

Network mode 7-2,7-8,7-10,7-21

Transmit Data Registers (TX0–TX2) 7-14,7-33

Normal mode 7-2,7-10,7-20,7-21

Transmit Enable (TE) 7-18

On-Demand mode 7-10,7-15,7-20,7-21

Transmit Shift Registers 7-30

operating mode 7-6,7-10,7-21

Transmit Slot Mask Register (TSM)

polling 7-7

programming sheet B-34

Port Control Register (PCR) 7-6,7-36

Transmit Slot Mask Registers (TSMA and

Port Control Register C (PCRC) 7-36

TSMB) 7-14,7-33

Port Control Register D (PCRD) 7-36

TX clock 7-11

Port Data Register (PDR) 7-38

variable prescaler 7-16

Port Data Register C (PDRC) 7-38

word length frame sync 7-12

Port Data Register D (PDRD) 7-38

word length frame sync timing 7-12

Port Direction Register (PRR) 7-37

Enhanced Synchronous Serial Interface 0 (ESSI0)

Port Direction Register C (PRRC) 7-37

GPIO 5-6

Port Direction Register D (PRRD) 7-37

signals 2-23

prescale divider 7-16

Enhanced Synchronous Serial Interface 1 (ESSI1)

programming model 7-14

GPIO 5-6

receive data interrupt request 7-28

signals 2-25

Receive Data Register (RX) 7-14,7-30

Enhanced Universal Bus mode 6-15

Receive Shift Register 7-29

EOM byte 4-12

receive shift register clock output 7-4

ESSI 1-12

Receive Slot Mask Register (RSM)

ESSI0 Interrupt Priority Level (S0L) bits 4-16

programming sheet B-34

ESSI1 Interrupt Priority Level (S1L) bits 4-16

Receive Slot Mask Registers (RSMA and

expansion memory 3-1

RSMB) 7-14,7-35

Extended Mode Register (EMR) 4-7

reset 7-6

Arithmetic Saturation Mode (SM) 4-7

RX clock 7-11

Cache Enable (CE) 4-8

RX frame sync 7-11

Core Priority (CP) 4-7

RX frame sync pulses active 7-11

DO FOREVER (FV) Flag 4-8

select source of clock signal 7-22

Rounding Mode (RM) 4-7

Serial Clock (SCK), ESSI 7-3

Sixteen-bit Arithmetic Mode (SA) 4-8

Serial Control 0 (SC00 and SC10) 7-4

Extension (E) bit 4-11

Serial Control 1 (SC01 and SC11) 7-4

External (EXTAL) clock input 2-5

Serial Control 2 (SC02 and SC12) 7-6

external address bus 2-6

Serial Input Flag (IF0) 7-4

external bus control 2-6

Serial Output Flag 0 (OF0) bit 7-4

External Bus Disable (EBD) bit 4-15

Serial Output Flags (OF0–OF1) 7-18

external data bus 2-6

Serial Receive Data (SRD) 7-3

external memory expansion port 2-6

Serial Transmit Data (STD) 7-3

F

signals 2-1

SPI protocol 7-2

Fast Back-to-Back Capable (FBBC) bit 6-66

Synchronous mode 7-4,7-11,7-13

Synchronous Serial Interface Status Register

frame rate divider 7-10

Frame Rate Divider Control (DC) bits 7-16

(SSISR) 7-14,7-28

bit definitions 7-28

frame sync

generator 7-17

Receive Data Register Full (RDF) 7-28

length 7-12

Receiver Frame Sync Flag (RFS) 7-29

selection 7-11

Receiver Overrun Error Flag (ROE) 7-28

signal 7-7,7-10,7-18

Serial Input Flag 0 (IF0) 7-29

Serial Input Flag 1 (IF1) 7-29

Frame Sync Length (FSL) bits 7-22

Frame Sync Polarity (FSP) bit 7-22

Transmit Data Register Empty (TDE) 7-28

Frame Sync Relative Timing (FSR) bit 7-22

Transmit Frame Sync Flag (TFS) 7-29

Framing Error Flag (FE) bit 8-17

Transmitter Underrun Error Flag (TUE) 7-28

functional signal groups 2-2

Synchronous/Asynchronous (SYN) bit 7-11

 

 

 

 

Index-5

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Motorola DSP56301 user manual Index-5
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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