Motorola DSP56301 user manual HI32 Control Register Hctr Read/Write

Programming Sheets

Application:	Date:
	Programmer:

Sheet 5 of 10

Host Processor (HI32)

Target Wait State Disable, Bit 19

0 = PCI wait states enabled

1 = PCI wait states disabled Modes: PCI only

Host Semaphores, Bits 16–14

Serve only as read/write repository for semaphores when multiple master hosts are used.

Modes: UBM and PCI

Host Receive Data Transfer Format, Bits 12–11

HI32 bus data transfer formats, as follows:

DSP-to-PCI Host (DCTR[HM] = $1)

00 32-bit data mode

013 LSBs in DTXS/HRXS right-aligned/zero extended to HAD[31–0] MSB

103 LSBs in DTXS/HRXS left-aligned /zero filled to HAD[31–0] LSB

113 LSBs in DTXS/HRXS right-aligned/sign extended in HAD[31–0] MSB

DSP-to-UB Host (DCTR[HM] = $2 or $3)

0024-bit data mode: DTXS to HRXS and HD[23–0]

012 LSB data in DTXS to HRXS and HD[15–0]

102 LSB data in DTXS to HRXS and HD[15–0]

112 MSB data in DTXS to HRXS and HD[15–0]

Note: LSB = least significant byte; MSB = most significant byte

Modes: UBM and PCI

Host Transmit Data Transfer Format, Bits 9–8

HI32 bus data transfer formats, as follows: PCI Host-to-DSP (DCTR[HM] = $1)

00 32-bit data mode

013 LSBs from HAD[23–0] to HTXR/DRXR LSBs

103 LSBs from HAD[23–0] to HTXR/DRXR LSBs

113 MSBs from HAD[31–8] to HTXR/DRXR LSBs

Note: Address insertion is affected the same way as the data in PCI mode.

UB Host-to-DSP (DCTR[HM] = $2 or $3)

00 24-bit data mode: HD[23–0] to 3 LSBs HTXR/DRXR

01HD[15–0] to 3 LSBs HRXS (right-aligned/zero extended) to DRXR

10HD[15–0] to 3 LSBs HRXS (right-aligned/sign extended) to DRXR

11HD[15–0] to 3 LSBs HRXS (left aligned/zero filled) to DRXR

Note: LSB = least significant byte; MSB = most significant byte

Modes: UBM and PCI

Slave Fetch Type, Bit 7

0 = Fetch mode

1= Pre-fetch mode Modes: UBM and PCI

DMA Enable, Bit 6

0 = DMA accesses disabled

1 = DMA accesses enabled Modes: UBM only

Host Flags, Bits 5–3

Used for host-to-DSP communication

Set or cleared by host, visible to DSP

Receive Request Enable, Bit 2

0 = Receive requests disabled

1 = Receive requests enabled Modes: UBM only

Transmit Request Enable, Bit 1

0 = Transmit requests disabled

1 = Transmit requests enabled Modes: UBM only

31		30 29 28			27 26 25 24				23 22 21 20				19 18 17 16				15 14 13 12				11 10		9	8			7	6	5	4	3	2	1	0
	*	*	*	*	*	*	*	*	*	*	*	*	TWSD	*0	*0	HS2	HS1	HS0	*0	HRF1	HRF0	*0	HTF1		HTF0		SFT	DMAE	HF2	HF1	HF0	RREQ	TREQ	*
	0	0	0	0	0	0	0	0	0	0	0	0																						0
	HI32 Control Register (HCTR)										Read/Write													*		= Reserved, Program as 0
	Reset = $00000000
									Figure B-14.HI32 Control Register (HCTR)
B-26													DSP56301 User’s Manual