ESSI Programming Model

Table 7-4.ESSI Control Register B (CRB) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

 

 

 

 

 

 

 

 

4

SCD2

0

Serial Control Direction 2

 

 

 

Controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an

 

 

 

output; when SCD2 is cleared, SC2 is an input.

 

 

 

Note: Programming the ESSI to use an internal frame sync (that is,

 

 

 

SCD2 = 1 in CRB) causes the SC2 and SC1 signals to be

 

 

 

programmed as outputs. However, if the corresponding

 

 

 

multiplexed pins are programmed by the Port Control Register

 

 

 

(PCR) to be GPIOs, the GPIO Port Direction Register (PRR)

 

 

 

chooses their direction. The ESSI uses an external frame sync if

 

 

 

GPIO is selected. To assure correct operation, either program

 

 

 

the GPIO pins as outputs or configure the pins in the PCR as

 

 

 

ESSI signals. The default selection for these signals after reset is

 

 

 

GPIO. This note applies to both ESSI0 and ESSI1.

 

 

 

 

3

SCD1

0

Serial Control Direction 1

 

 

 

In Synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 = 0),

 

 

 

or in Asynchronous mode (SYN = 0), SCD1 controls the direction of the

 

 

 

SC1 I/O signal. When SCD1 is set, SC1 is an output; when SCD1 is

 

 

 

cleared, SC1 is an input. When TE2 is set, the value of SCD1 is ignored

 

 

 

and the SC1 signal is always an output.

 

 

 

 

2

SCD0

0

Serial Control Direction 0

 

 

 

In Synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0),

 

 

 

or in Asynchronous mode (SYN = 0), SCD0 controls the direction of the

 

 

 

SC0 I/O signal. When SCD0 is set, SC0 is an output; when SCD0 is

 

 

 

cleared, SC0 is an input. When TE1 is set, the value of SCD0 is ignored

 

 

 

and the SC0 signal is always an output.

 

 

 

 

1

OF1

0

Serial Output Flag 1

 

 

 

In Synchronous mode (SYN = 1), when transmitter 2 is disabled (TE2 = 0),

 

 

 

the SC1 signal is configured as ESSI flag 1. When SCD1 is set, SC1 is an

 

 

 

output. Data present in bit OF1 is written to SC1 at the beginning of the

 

 

 

frame in Normal mode or at the beginning of the next time slot in Network

 

 

 

mode.

 

 

 

 

0

OF0

0

Serial Output Flag 0

 

 

 

In Synchronous mode (SYN = 1), when transmitter 1 is disabled (TE1 = 0),

 

 

 

the SC0 signal is configured as ESSI flag 0. When SCD0 is set, the SC0

 

 

 

signal is an output. Data present in Bit OF0 is written to SC0 at the

 

 

 

beginning of the frame in Normal mode or at the beginning of the next time

 

 

 

slot in Network mode.

 

 

 

 

Enhanced Synchronous Serial Interface (ESSI)

7-23

Page 220 Page 222
Page 221
Image 221
Motorola DSP56301 user manual Serial Control Direction, OF1, Serial Output Flag, OF0
Page 220 Page 222

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
Top Page Image Contents