Host-Side Programming Model

Table 6-24.Host Command Vector Register (HCVR) Bit Definitions (Continued)

Bit

Bit Name

Reset Value

Mode

Description

Number

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

HC

0

UBM

Host Command

 

 

 

PCI

Used by the host processor to handshake the execution of host

 

 

 

 

command interrupt requests. Normally, the host processor sets

 

 

 

 

HC to request a host command interrupt from the DSP56300 core.

 

 

 

 

When the DSP56300 core acknowledges the host command

 

 

 

 

interrupt request, HI32 hardware clears the HC bit. The host

 

 

 

 

processor can read the state of HC to determine when the host

 

 

 

 

command request is serviced. The host processor cannot clear

 

 

 

 

HC. Setting HC causes host command pending (HCP) to be set in

 

 

 

 

the DSR. The host can write HC and HV in the same write cycle if

 

 

 

 

desired. If HC is set:

νIn the PCI mode: The HI32 is a target in a write data phase to the HCVR. It deasserts HTRDY and inserts up to eight PCI wait cycles until HC is cleared.

νIn a Universal Bus mode: In a write transaction to the HCVR, the HI32 slave deasserts HTA until HC is cleared.

6.8.4Host Master Receive Data Register (HRXM)

The HRXM is the output stage of the master DSP-to-host data path FIFO for DSP-to-host data transfers. Neither the DSP56300 core nor the host can access the HRXM. The HRXM transfers the data to the HI32 data pins via the data transfer format converter (HDTFC). The value of the DPMC[FC] bits define which bytes of the HRXM are output to the pins and their alignment. (See Section 6.3.2, DSP-To-Host Data Path, on page 6-7and

Table 6-3,HI32 (PCI Master Data Transfer Formats, on page 6-8).

In PCI mode (DCTR[HM] = $1), the DSP56300 core can clear the HI32 master-to-host bus data path and empty HRXM by setting the DPCR[CLRT] bit. In PCI DSP-to-host data transfers via the HRXM, all four byte lanes are driven with data, in accordance with the FC[1–0] bits, regardless of the value of the byte enable pins ( HC3/HBE3-HC0/HBE0). Hardware, software and personal software resets empty the HRXM.

6.8.5Host Slave Receive Data Register (HRXS)

The HRXS is the output stage of the slave DSP-to-host data path FIFO for DSP-to-host data transfers. The DSP56300 core cannot access HRXS. The HRXS contains valid data when the HSTR[HRRQ] bit is set. Emptying the HRXS by host processor reads clears HSTR[HRRQ].

The HRXS transfers the data to the HI32 data pins via the data transfer format converter (HDTFC). The value of the HCTR[HRF] bits define which bytes of the HRXS are output to

Host Interface (HI32)

6-61

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Motorola DSP56301 user manual Host Master Receive Data Register Hrxm, Host Slave Receive Data Register Hrxs, Host Command
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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