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Motorola DSP56301 SCI Data Registers, SCI Receive Register SRX, SCI Receive Data Shift Register

Models: DSP56301

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SCI Programming Model

8.6.4SCI Data Registers

The SCI data registers are divided into two groups: receive and transmit, as shown in Figure

8-7. There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel

Receive Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX or STXA) and a parallel-to-serial Transmit Shift Register.

23

16 15

8

7

0

SRX

SRX

SRX

SCI Receive Data Register High (Read Only) SCI Receive Data Register Middle (Read Only) SCI Receive Data Register Low (Read Only)

RXD

SCI Receive Data Shift Register

Note: SRX is the same register decoded at three different addresses.

(a) Receive Data Register

23

16 15

8

7

0

STX

STX

STX

SCI Transmit Data Register High (Write Only) SCI Transmit Data Register Middle (Write Only) SCI Transmit Data Register Low (Write Only)

	SCI Transmit Data Shift Register
									TXD
									TXD

23	16 15		8	7			0
23	16 15		8	7			0
								SCI Transmit Data Address Register (Write Only)
				STXA				SCI Transmit Data Address Register (Write Only)

Note: Bytes are masked on the fly.

1.STX is the same register decoded at four different addresses.

(b)Transmit Data Register

Figure 8-7.SCI Programming Model—Data Registers

8.6.4.1 SCI Receive Register (SRX)

Data bits received on the RXD signal are shifted into the SCI receive shift register. When a complete word is received, the data portion of the word is transferred to the byte-wide SRX. This process converts serial data to parallel data and provides double buffering. Double buffering promotes flexibility and increased throughput since the programmer can save (and process) the previous word while the current word is being received.

The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on

8-22	DSP56301 User’s Manual

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Motorola DSP56301 user manual SCI Data Registers, SCI Receive Register SRX, SCI Receive Data Shift Register

Contents

DSP56301 User’s Manual Revision 3, MarchJapan How to reach usUSA/EUROPE ASIA/PACIFICPage Page Contents Chapter Memory Configuration Chapter Core ConfigurationChapter Programming the Peripherals Chapter Host Interface HI32Chapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Chapter Triple Timer Module Chapter a Bootstrap Program Chapter B Programming ReferenceIndex Figures DSP56301 User’s ManualXii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables TablesEssi Clock Sources Manual Organization OverviewManual Conventions High True/Low True Signal ConventionsSignal/Symbol Logic State Signal State Voltage Ground2Ground PIN is a generic term for any pin on the chipDSP56300 Core Features Program RAM Instruction Data RAM Switch Size Cache Size CE = MS =Size Cache DSP56300 Core Functional Blocks Data ALUAddress Generation Unit AGU Data ALU RegistersMultiplier-Accumulator MAC Program Control Unit PCU PLL and Clock Oscillator Jtag TAP and OnCE ModuleDSP56301 Switch Memory Configuration Internal BusesOn-Chip Memory DMA Memory Expansion AreaExpansion Area Host Interface HI32 General-Purpose Input/Output Gpio signalsPeripherals Enhance Synchronous Serial Interface EssiTriple Timer Module Serial Communications Interface SCIName Description Order Number Related Documents and Web SitesDSP56301 Documentation DSP56300FM/ADEnhanced Synchronous Serial Interfaces ESSI0 DSP56301 Functional Signal GroupingsTimers JTAG/OnCE Port ESSI1See -2for a listing of the Host Interface/Port B Signals DSP56301Port a Host Interface/Port B Detail Signal Diagram Ground Signals PowerPower Inputs GroundClock Clock SignalsPhase-Lock Loop Signals PLLExternal Data Bus External Memory Expansion Port Port aExternal Address Bus External Bus ControlOutput Tri-stated Is an active-low output that is Signals are tri-statedArbitration is reset to the bus slave state Output Tri-stated Is asserted for half a clockCAS BclkSignal State Type During Signal Description Name Interrupt and Mode ControlInterrupt and Mode Control Nonmaskable Interrupt-AfterHost Interface HI32 10.Host InterfaceCommand 0-3/Byte Enable 0-3 -When the HI32 is programmed Hdak HBSHpar HperrHstop HserrHirq HWR11.Summary of HI32 Signals and Modes Signal PCI Mode Enhanced Universal Bus Mode Gpio Mode NameHAD11 HD3 HIO11 HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9HAD10 HD2 HIO10 HAD12 HD4 HIO1212.Host Port Pins HI32 PCIGpio Reserved Bus Command/Byte Enable Host Address BusHost Target Ready Host Data Bus Enable Host Initiator Ready Host Data Bus DirectionHost Device Select Host Select Acknowledge Parity Error DMA RequestBus Grant Host Address Enable Host Lock Bus StrobeHreq is deasserted in the same PCI Host System Error Host Interrupt RequestBus Request Host Transfer Acknowledge HstrHRD/HDS Hstop HWR/HRWHost Stop Host Write/Read-Write Initialization Device Select Host Read/Data StrobeHost Bus Clock Address/Data Multiplexed Bus Data BusHost Interrupt a Hardware ResetEnhanced Synchronous Serial Interface Active low, open drain output pinPC1 13.Enhanced Synchronous Serial InterfacePC0 PC2SRD0 SCK0PC3 PC4PD1 14.Enhanced Serial Synchronous InterfacePD0 PD2SRD1 SCK1PD3 PD4Timers Serial Communications Interface SCI15.Serial Communication Interface Timer 1 Schmitt-Trigger Input/Output- When Timer 16.Triple Timer SignalsTimer 0 Schmitt-Trigger Input/Output- When Timer Timer 2 Schmitt-Trigger Input/Output- When timerSignal Name Type State During Signal Description Reset Jtag and OnCE Interface17.JTAG/OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Memory Configuration Program Memory SpaceMemory Switch Modes-Program Memory Internal Program MemoryInstruction Cache Memory Configuration Program Bootstrap ROMMemory Switch Modes-X Data Memory Data Memory SpaceMemory Switch Modes-Y Data Memory Internal I/O Space-X Data MemoryInternal Y Data Memory Dynamic Memory Configuration Switching External I/O Space-Y Data MemoryDSP56301 RAM Configurations Sixteen-Bit Compatibility Mode ConfigurationInternal Memory Configuration Summary DSP56301 RAM Address Ranges by ConfigurationDefault Memory MapsRAM 16-Bit Space With Default RAM 0, 0 None 64K $000-$FFF $000-$7FF16M $000-$800 $000-$BFF16-Bit Space With Switched Program RAM 0, 1 None 64K $000-$7FF $000-$BFFInstruction Cache Enabled 1, 0 $000-$BFF $000-$7FF Not addressable16-Bit Space With Instruction Cache Enabled 1, 0 Addressable $000-$3FF $000-$BFF Not addressable$0400 $0000 Core Configuration Core ConfigurationDSP56301 Operating Modes Reset Description VectorOperating Modes ModeOperating Mode Definitions Mode DescriptionAddress attributes selected default Low. The DSP56301 is written with 24-bit-wide wordsDSP Clkout rate must be 5/3 of the PCI clock Bootstrap Program Central Processor Unit CPU Registers Status Register SRDMA OMR Do Forever Flag Cache EnableSixteen-Bit Arithmetic Mode Do Loop FlagSixteen-Bit Compatibility Mode Interrupt Mask Scaling ModeScaling Rounding Bit SEquation Mode Priority Exceptions Exceptions Masked PermittedExtension Bit Number Bit Name Reset Value Description LimitScaling Mode Integer Portion UnnormalizedStack Extension Enable Operating Mode Register OMROperating Mode Register OMR Bit Definitions Stack Extension Wrap FlagAsynchronous Bus Arbitration Enable Address Trace EnableAddress Attribute Priority Disable Stack Extension Overflow FlagBus Release Timing Cache Burst Mode EnableMemory Switch Mode Synchronize SelectExternal Bus Disable Configuring InterruptsBit Number Bit Name Reset Value Description Stop Delay Mode Chip Operating ModeInterrupt Priority Registers Iprc and Iprp Interrupt Table Memory Map Interrupt Priority Level BitsInterrupt Sources VBA$1E VBA$1AVBA$1C VBA$2AProcessing Interrupt Source Priorities Within an IPL Interrupt Source Priorities Within an IPLPriority Interrupt Source TIMER0 compare interrupt Host command interruptTIMER0 overflow interrupt TIMER1 overflow interruptPLL Control Register Pctl PLL Control Register Pctl Bit DefinitionsBus Interface Unit BIU Registers Bus Control RegisterBus Area 2 Wait State Control Bus Default Area Wait State ControlBus Area 3 Wait State Control Bus Area 1 Wait State ControlBRF3 BRF2 BRF1 Dram Control Register DCRBRP BRF7 BRF6 Bstr Bren BME Bple BPS110.DRAM Control Register DCR Bit Definitions Bus Row Out-of-page Wait States Bus Page Logic EnableBus Dram Page Size Bus Column In-Page Wait StateAddress Attribute Registers AAR0-3 Bus Address to CompareBus Number of Address Bits to Compare Bus X Data Memory Enable Bus Packing EnableBus Y Data Memory Enable Bus Program Memory EnableDcon DMA Control Registers 5-0 DCR5-0DIE DTM2 DTM1 DTM0 DAM5 DAM4 DAM3 DAM2 DAM1 DAM0DTM2-0 Trigger Cleared Transfer Mode After DMA Interrupt EnableDMA Transfer Mode 12.DMA Control Register DCR Bit DefinitionsDMA address generation logic, buses, and so forth Number ValueDMA Channel Priority DPR1-0 Channel PriorityDMA Continuous Mode Enable OMR CDP1-0 CP1-0 Core PriorityDcon Three-Dimensional Mode DMA Request SourceDRS4-0 Requesting Device Device Identification Register IDR DDS1 DDS0DSS1 DSS0 Version Information Design Center Jtag Identification ID RegisterJtag Boundary Scan Register BSR Number Identity See NoteJtag Boundary Scan Register BSR DSP56301 User’s Manual Peripheral Initialization Steps Programming the PeripheralsPolling Mapping the Control RegistersData Transfer Methods Data MemoryInterrupts General-Purpose Input/Output Gpio 3 DMAAdvantages and Disadvantages Port B Signals and Registers Host Interface/Port B Detail Signal DiagramPort C Signals and Registers Port D Signals and RegistersPort E Signals and Registers Triple Timer Signals and Registers Timer GpioGeneral-Purpose Input/Output Gpio DSP56301 User’s Manual Features Host Interface HI32HI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview DSP DMA Data Bus DSP Global Data Bus PCI Configuration SpaceDSP-Side Registers Data transfer format converterData Transfer Paths Host-to-DSP Data PathDSP-To-Host Data Path FC1 FC0 HI32 PCI Master Data Transfer FormatsDpmc Two least significant bytes of two HrxmTransmit Data Transfer Format HctrHTF1 HTF0 HRF Receive Transfer Data FormatsDSP to Host Data Transfer Format Three least significant Hrxs bytesReceive Transfer Data Formats DSP-Side Operating Modes Reset StatesType Entered when Description HRST/HRSTHI32 Mode Terminate and Reset Dctrhm = $0PCI Mode Dctrhm = $1 PCIExample 6-1. PCI /DMA Throughput 32-Bit Multfactor Gpio Mode Dctrhm = $4 Self-Configuration Mode Dctrhm = $5Example 6-3. Self-Configuration Procedure for PCI Mode Host Port Pins PCI Bus Universal Bus ModeHost Port Pin Functionality DSP56301 ISA Master SlaveMemory Register Address Mode HI32 DSP-Side Programming ModelHI32 Programming Model, DSP Side Mode Description Value DSP Control Register DctrBit Number Bit Name 10.DSP Control Register Dctr Bit Definitions Host Transfer Acknowledge Polarity Host Data Strobe ModeHtap Host Read/Write PolarityHost Command Interrupt Enable Slave Receive Interrupt EnableSlave Transmit Interrupt Enable DSP PCI Control Register Dpcr11.DSP PCI Control Register Dpcr Bit Definitions Insert Address EnableReceive Buffer Lock Enable IAEForce Master Wait State DisableMaster Access Counter Enable HserrTransaction Abort Interrupt Enable Transfer Complete Interrupt EnableTransaction Termination Interrupt Enable Parity Error Interrupt EnableDSP PCI Master Control Register Dpmc BL4BL1 BL0 A PCI DSP-to-Host transaction 12.DSP PCI Master Control Register Dmpc Bit DefinitionsData Transfer Format Control A PCI Host-to-DSP transactionPCI Data Burst Length DSP PCI Transaction Address HighBE2 BE1 DSP PCI Address Register Dpar13.DSP PCI Address Register Dpar Bit Definitions AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0DSP PCI Transaction Address Low PCI Bus CommandC3-0 Command Type AR1 AR014.DSP Status Register DSR Bit Definitions Bit Bit Name Reset Mode Description Number ValueDSP Status Register DSR 2322212019181716Srrq UBM Slave Receive Data Request14. DSP Status Register DSR Bit Definitions Mode Description Number ValueHost Command Pending Slave Transmit Data RequestRdcq MDT Hdtc Trty Tdis TAB MAB DSP PCI Status Register Dpsr15.DSP PCI Status Register Dpsr Bit Definitions Aper Marq Mrrq Mtrq MWSPCI Time Out Termination Master Data TransferredPCI Host Data Transfer Complete PCI Target RetryPCI Target Disconnect PCI Data Parity ErrorPCI Address Parity Error PCI Target AbortPCI Master Wait States DSP Receive Data Fifo Drxr15. DSP PCI Status Register Dpsr Bit Definitions PCI Master Receive Data RequestDSP Master Transmit Data Register Dtxm DSP Slave Transmit Data Register DtxsDSP Host Port Gpio Direction Register Dirh DSP Host Port Gpio Data Register Dath16.DATH and Dirh Functionality Host-Side Programming Model 17.HI32 Programming Model, Host-Side RegistersMemory Register Host-Side Programming Model HC3/HBE3-HC0/HBE0 18.PCI Bus CommandsExecuted as Command Type Ignored20. Host-Side Registers PCI Configuration Address Space 21. Host-Side Registers Universal Bus Mode Address Space19. Host-Side Registers PCI Memory Address Space 1 HI32 Control Register Hctr 13.Host Interface Control Register Hctr22.Host Interface Control Register Hctr Bit Definitions Bit Bit Name Reset Mode Description NumberTarget Wait State Disable Twsd PCIHost Receive Data Transfer Format Host Transmit Data Transfer Format Inserted Address SFT UBMSlave Fetch Type Reset, and Strq and Hstrhrrq are cleared Universal Bus mode Fetch SFT =Cleared when the DSP56300 core writes to Data path is lost when the reset state isDmae UBM Dmae HaenHirq Dmae Treq Rreq Receive Req uest EnableRreq UBM Hirq Pin Hdrq pinTrdy Host Interface Status Register HstrHreq Hint HF5 HF4 HF3 UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCIHost interrupt a 23.Host Interface Status Register Hstr Bit DefinitionsHost Request Treq Rreq HreqHost Receive Data Request Host Transmit Data RequestTransmitter Ready Host Command Vector Register Hcvr 15.Host Command Vector Register HcvrBit Bit Name Reset Value Mode Description Number 24.Host Command Vector Register Hcvr Bit DefinitionsHost Command Vector Hnmi UBMHost Master Receive Data Register Hrxm Host CommandWhen the DSP56300 core acknowledges the host command Host Slave Receive Data Register HrxsHost Transmit Data Register Htxr PCI Mode Dctrhm = $1 Universal Bus mode Dctrhm = $2 or $3DPE SSE RMA RTA STA Device ID/Vendor ID Configuration Register CDID/CVIDStatus/Command Configuration Register CSTR/CCMR DPR FbbcSignalled Target Abort Detected Parity ErrorSignaled System Error Received Master AbortParity Error Response System Error EnableWait Cycle Control hardwired to zero Bus Master EnableClass Code/Revision ID Configuration Register CCCR/CRID HT7-0 Header Type hardwired to $00HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 Read-only bits that identify the layout of bytes $10-$3FLatency Timer High Cache Line SizeCcls PM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Space Base Address Configuration Register CbmaUniversal Bus Mode Base Address Memory Base Address High/LowPre-Fetch Hardwired to zero 29. Memory Space Base Address Configuration Register CbmaMemory Base Address Low Hardwired to zeros Memory Space Hardwired to zerosExample 6-5. Code for Setting the Csid IL1 IL0 Interrupt Line-Interrupt Pin Configuration RegisterCILPIL5 IL4 MaxlatDctr Hcie HI32 Programming Model/Quick ReferenceHS PH PS UBM HrspDpcr Mtie ClrtRble DSR HCP DpmcDpar HactHdtc Dpsr AperDper RdcqISA/EISA TreqDmae SFTHrxm HcvrHnmi HrxsChty Ccmr RMACccr Cbma MSITsmb TX0 CRA GDB DDB RclkRsma Rsmb Tsma Tclk STD SC0Essi Enhancements Serial Receive Data Signal SRD Essi Data and Control SignalsSerial Transmit Data Signal STD Serial Clock SCKSerial Control Signal SC0 Serial Control Signal SC1Mode and Signal Definitions Control Bits Essi SignalsSYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Operation Serial Control Signal SC2Essi After Reset InitializationExceptions Operation Write data to all enabled transmit registers Normal/Network/On-Demand Mode Selection Operating Modes Normal, Network, and On-DemandFrame Sync Signal Format Synchronous/Asynchronous Operating ModesFrame Sync Selection Frame Sync Length for Multiple Devices Word Length Frame Sync and Data Word TimingFrame Sync Polarity Byte Format LSB/MSB for the Transmitter FlagsWL2 WL1 WL0 ALC Essi Programming ModelEssi Control Register a CRA PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0Word Length Control Essi Control Register a CRA Bit DefinitionsSelect SC1 Essi Word Length SelectionPrescaler Range Alignment ControlFrame Rate Divider Control Prescale Modulus SelectRclock CRBTE1 CRBOF0 SSISRIF0Crbsyn = TclockOF1 OF0 Essi Control Register B CRBShfd ESSI0 X$FFFFB6, ESSI1 X$FFFFA6Essi Control Register B CRB Bit Definitions Transmit 0 Enable Transmit Interrupt EnableReceive Enable TIEMode Select Transmit 1 EnableTransmit 2 Enable Synchronous/AsynchronousFSL1 FSL0 Serial Output Flag Serial Control DirectionOF1 OF0Serial Clock RX, TX Frame Sync RX, TX Serial Data Serial Clock RX Frame Sync RX Serial DataTX Frame Sync TX Serial Data CRB SYN Bit Operation Essi BitBit Operation SSI Control Register B CRB READ/WRITEReceiver Interrupt or DMA Request and Flags Set Frame Sync FSL0 = 0, FSL1 = Data Out Flags Frame Sync FSL0 = 0, FSL1 = Data FlagsEssi Status Register Ssisr Receiver Overrun Error FlagTransmitter Underrun Error Flag Receive Data Register FullTransmit Frame Sync Flag Essi Receive Shift RegisterReceive Frame Sync Flag Serial Input FlagEssi Receive Data Register RX Essi Transmit Shift RegistersReceive Registers Transmit RegistersLeast Significant Transmit Middle Byte Transmit Low Byte Register 24 BitWL0 MSBTransmit Slot Mask Registers TSMA, Tsmb Essi Transmit Data Registers TX2-0Essi Time Slot Register TSR TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS015.ESSI Transmit Slot Mask Register B Tsmb RS1 RS0 Receive Slot Mask Registers RSMA, RsmbRS7 RS6 RS15 RS14 RS13 RS12 RS11 RS10Gpio Signals and Registers Port Control Registers Pcrc and PcrdEssi Port Signal Configurations Port Direction Registers Prrc and PrrdESSI0/ESSI1 Port Data Registers Pdrc and Pdrd 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFADSerial Communication Interface SCI Serial Communication Interface SCISynchronous Mode Asynchronous ModeMultidrop Mode Address Mode Wakeup I/O SignalsWired-OR Mode Transmitting Data and Address CharactersReceive Data RXD Transmit Data TXDSCI Serial Clock Sclk Reie Sckp Stir Tmie TIE RIE Ilie SCI After ResetSCI Registers After Reset Woms RWU Wake SBK SsftdSCI Initialization Preamble, Break, and Data Transmission Priority Bootstrap Loading Through the SCI Boot Mode 2 or a ExceptionsSCI Programming Model Bit Asynchronous 1 Start, 8 Data, 1 Stop Bit Synchronous Data Shift Register ModeWDS2 WDS1 WDS0 Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 StopSCI Data Word Formats Ssftd = 0 SCI Control Register SCR ReieStir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 SCI Receive Interrupt Enable Timer Interrupt EnableSCI Transmit Interrupt Enable Idle Line Interrupt EnableReceiver Enable Wired-OR Mode SelectWoms Send Break Receiver Wakeup EnableWakeup Mode Select SCI Shift DirectionMode Word Formats Word SelectWDS1 WDS0 SCI Status Register SSR SCI Status Register SCI Status Register SSR Bit DefinitionsIdle Rdrf Tdre Trne Idle Line Flag TdreTransmitter Empty TCM RCM SCI Clock Control Register SccrTCM RCM SCP COD SclkCD11-0 Bit CounterDivide by Sckp = 0 + Sckp =RX, TX Data Ssftd = X1 Clock X16 Clock Sckp =SCI Data Registers SCI Receive Register SRXSCI Receive Data Shift Register SCI Transmit Register STX Port E Control Register Pcre PE2 PE1 PE0Sclk TXD RXD PRRE1 PRRE0 Port E Direction Register PrrePort E Data Register Pdre PDRE1 PDRE0Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer ModuleGDB Triple Timer Module Block DiagramIndividual Timer Block Diagram TpcrTimer After Reset Timer Module Block DiagramTimer Initialization Timer ExceptionsTCSR0 Tcie TC3 TC2 TC1 TC0 Triple Timer ModesTimer Gpio Mode TIOMode 0 internal clock, no timer output TRM = TLRTCR Tcpr Timer Pulse Mode Mode 1 internal clock TRM =Output Pulse width = timer clock Period Toggle Timer Timer Toggle ModeMode 2 internal clock TRM = 1 first event = write preload = write compare Clock CLK/2 or prescale CLKMode 2 internal clock TRM = = write preload= write compare Clock CLK/2 or prescale CLK Input External Timer Event Counter ModeMode 3 internal clock TRM = TIO Cpuclk +10.Event Counter Mode, TRM = = write compare ClockInput Signal Measurement ModesMeasurement Input Width Mode Input width MeasurementMode 4 internal clock TRM = Mode 4 internal clock TRM = 1 first eventFirst event = write preload = write compare Measurement Input Period ModeMode 5 internal clock TRM = Input period Measurement InternalCounting, does May occur TOF=1Reads TCR period Interrupt Service reads TCR delay = M N clock periods Measurement Capture ModeMode 6 internal clock TRM = InternalPulse Width Modulation PWM, Mode PWMPulse width modulation Mode 7 internal clock TRM = 16.Pulse Width Modulation Toggle Mode, TRM =17.Pulse Width Modulation Toggle Mode, TRM = Pulse Watchdog Watchdog Pulse ModeWatchdog Modes Output InternalMode 9 internal clock TRM = Software does not reset watchdog timer watchdog times out= write preload First event Watchdog Output Watchdog Toggle ModeMode 10 internal clock TRM = ToggleDMA Trigger Triple Timer Module Programming ModelSpecial Cases Prescaler Counter23 22 21 20 19 18 17 Timer Prescaler LoadRegister Tplr Tplr = $FFFF83PS1 PS0 Timer Prescaler Load Register TplrPrescaler Source Prescaler Preload ValueTCF TOF PCE Timer Prescaler Count Register TpcrTimer Control/Status Register Tcsr TRM INVPrescaler Clock Enable Timer Compare FlagTimer Overflow Flag Data OutputTimer Reload Mode DirectionInverter Timer Control Number FunctionTimer Enable Timer Compare Interrupt EnableTimer Overflow Interrupt Enable TIO Programmed as Input TIO Programmed as Output Mode INV =Timer Load Register TLR Pulse generated by Timer has Timer has negativePositive polarity Timer Compare Register Tcpr Timer Count Register TCRAppendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Chapter B Programming ReferenceTable B-1.Guide to Programming Sheets Internal I/O Memory Map Table B-2. Internal I/O Memory Map X Data MemoryBit Address Register Name Table B-2.Internal I/O Memory Map X Data Memory Peripheral Bit Address Register Name$FFCB $FFFFCB $FFCD $FFFFCD$FFCC $FFFFCC $FFCA $FFFFCA$FFBA $FFFFBA Essi $FFBC $FFFFBC$FFBB $FFFFBB $FFB9 $FFFFB9$FFAA $FFFFAA Essi $FFAC $FFFFAC$FFAB $FFFFAB $FFA9 $FFFFA9$FFFF90 $FFFF92$FFFF91 $FF8F $FFFF8FInterrupt Sources and Priorities Table B-3. Interrupt SourcesVBA$6C Table B-3.Interrupt SourcesVBA$6A VBA$6ENonmaskable Host Command Interrupt Table B-4.Interrupt Source Priorities Within an IPLESSI0 receive last slot interrupt Programming Sheets Figure B-1.Status Register SRMemory Switch Mode External Bus DisableStop Delay Burst Mode EnableIrqb Mode Irqd ModeIrqc Mode Irqa ModeTriple Timer IPL Host IPLInterrupt Priority Register Iprp $FFFFFE Read/Write PLL Control Register Pctl $FFFFFD Read/Write Crystal Range Bit XtlrBus Request Hold, Bit Default Area Wait Control, BitsBus Control Register BCR $FFFFFB Read/Write Bus Lock Hold, BitDram Control Register DCR $FFFFFA Read/Write Bus X Data Memory Enable, Bit Bus Packing Enable, BitBus Y Data Memory Enable, Bit Bus Program Memory Enable, BitReset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/Write DMA Control Registers DCR5-DCR0DSP Control Register Dctr Read/Write Address X FFFFC5 Application= Enables master receive interrupts DSP PCI Control Register Dpcr Address XFFFFC6 Read/WriteFigure B-12.DSP PCI Master Control Register Dpmc PCI Bus Command, Bits Figure B-13.DSP PCI Address Register DparHI32 Control Register Hctr Read/Write HI32 Command Vector Register Hcvr Read/Write Host Non-Maskable Interrupt, BitSignalled Target Abort, Bit Detected Parity Error, BitSignaled System Error, Bit System Error Enable, BitHeader Type, Bits Latency Timer High, BitsRead/Write Cache Line Size, BitsPCI Mode Base Address High, Bits Pre-fetch, Bit HI32 Memory Space Base Address Configuration Register CbmaReset = $00000000 Memory Space Indicator, BitSubsystem ID Register, Bits 31-16 Specifies the subsystem ID Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/Write ESSI1-X$FFFFA5 Read/WriteEssi Control Register B CRBx ESSI0-X$FFFFB6 Read/WriteESSI1-X$FFFFA6 Read/Write Essi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/WriteESSI1-X$FFFFA4 Read/Write ESSI1-X$FFFFA3 Read/WriteSCI Control Register SCR $FFFF9C Read/Write SCI Clock Control Register Sccr Address X$FFFF9B Read/Write Receiver Clock Mode/SourceClock Out Divider Figure B-25.Timer Prescaler Load Register Tplr Timer Prescaler Load Register Tplr $FFFF83 Read/WriteTimer Control/Status Register TCSR0$FFFF8F Read/Write TCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/WriteTimer Load Register TLR0-2 TLR0-X$FFFF8E Write Only TLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write OnlyPort B HI08 Host Data Direction Register Hddr X$FFFFC8 WriteHost Data Register HDR $FFFFC9 Write Port C Direction Register Prrc $FFFFBE Read/Write Port C ESSI0Port C Control Register Pcrc $FFFFBF Read/Write Port C Gpio Data Register Pdrc $FFFFBD Read/WritePort D Direction Register Prrd $FFFFAE Read/Write Port D ESSI1Port D Control Register Pcrd $FFFFAF Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/WritePort E Direction Register Prre $FFFF9E Read/Write Port E SCIPort E Control Register Pcre $FFFF9F Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/WriteProgramming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual