SCI Data Registers, SCI Receive Register SRX

SCI Programming Model

8.6.4SCI Data Registers

The SCI data registers are divided into two groups: receive and transmit, as shown in Figure

8-7. There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel

Receive Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX or STXA) and a parallel-to-serial Transmit Shift Register.

16 15

SRX

SCI Receive Data Register High (Read Only) SCI Receive Data Register Middle (Read Only) SCI Receive Data Register Low (Read Only)

RXD

SCI Receive Data Shift Register

Note: SRX is the same register decoded at three different addresses.

(a) Receive Data Register

16 15

STX

SCI Transmit Data Register High (Write Only) SCI Transmit Data Register Middle (Write Only) SCI Transmit Data Register Low (Write Only)

	SCI Transmit Data Shift Register
						TXD
						TXD

23	16 15	8	7	0
23	16 15	8	7	0
					SCI Transmit Data Address Register (Write Only)
			STXA		SCI Transmit Data Address Register (Write Only)

Note: Bytes are masked on the fly.

1.STX is the same register decoded at four different addresses.

(b)Transmit Data Register

Figure 8-7.SCI Programming Model—Data Registers

8.6.4.1 SCI Receive Register (SRX)

Data bits received on the RXD signal are shifted into the SCI receive shift register. When a complete word is received, the data portion of the word is transferred to the byte-wide SRX. This process converts serial data to parallel data and provides double buffering. Double buffering promotes flexibility and increased throughput since the programmer can save (and process) the previous word while the current word is being received.

The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on

8-22	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 SCI Data Registers, SCI Receive Register SRX, SCI Receive Data Shift Register

Models: DSP56301

8.6.4SCI Data Registers

SCI Receive Data Shift Register

Figure 8-7.SCI Programming Model—Data Registers

8.6.4.1 SCI Receive Register (SRX)

DSP56301 specifications