Data Transfer Paths

HRXS. Each time the host reads a 32-bit word from the HRXS, the 32-bits of significant data located in two locations of the slave DSP-to-host data path (DTXS and HRXS) are output.

The DSP side of the DSP-to-host data FIFOs is described in the following pages. For a detailed description of the host side, see Section 6.8.4, Host Master Receive Data Register (HRXM), on page 6-61and Section 6.8.5, Host Slave Receive Data Register (HRXS), on page 6-61.

Table 6-3.HI32 (PCI Master Data Transfer Formats

DPMC

DSP-to-PCI Host

PCI Host-to-DSP

Register

 

 

Data Transfer Format

Data Transfer Format

FC1

FC0

 

 

 

 

 

 

 

 

 

 

0

0

The two least significant bytes of two HRXM

All 32 PCI data bits are written to the HTXR as two

 

 

locations are output.

zero extended 16-bit words.

X

GDB/MDDB

HI32

GDB/MDDB

HI32

 

 

X

DTXM

$0

DRXR

X

HRXM

$0

HTXR

 

HDTFC

 

HDTFC

 

PCI bus

 

PCI bus

0

1 The three least significant HRXM bytes are output

The three least significant PCI data bytes are

 

right aligned and zero extended.

written to the HTXR.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HI32

 

 

 

 

 

 

GDB/MDDB

 

HI32

 

 

 

 

 

 

 

GDB/MDDB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DTXM

 

 

 

 

 

 

 

DRXR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HRXM

 

 

 

 

 

 

 

 

 

HTXR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HDTFC

 

 

 

 

 

 

 

 

 

HDTFC

 

 

$0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus

 

 

 

 

 

 

 

 

 

PCI bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$0

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0 The three least significant HRXM bytes are output

The three least significant PCI data bytes are

 

right aligned and sign extended.

written to the HTXR.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HI32

 

 

 

 

 

 

GDB/MDDB

 

HI32

 

 

 

 

 

 

 

GDB/MDDB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DTXM

 

 

 

 

 

 

 

DRXR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HRXM

 

 

 

 

 

 

 

 

 

HTXR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HDTFC

 

 

 

 

 

 

 

 

 

HDTFC

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

PCI bus

X

PCI bus

6-8

DSP56301 User’s Manual

Page 126
Image 126
Motorola DSP56301 user manual HI32 PCI Master Data Transfer Formats, Dpmc, FC1 FC0, Two least significant bytes of two Hrxm

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.