Bus Interface Unit (BIU) Registers

Table 4-9.Bus Control Register (BCR) Bit Definitions (Continued)

Bit

Bit Name

Reset Value

Description

Number

 

 

 

 

 

 

 

 

 

 

 

4–0

BA0W[4–0]

11111

Bus Area 0 Wait State Control

 

 

(31 wait

Defines the number of wait states (one through 31) inserted in each external

 

 

states)

SRAM access to Area 0 (DRAM accesses are not affected by these bits). Area 0 is

 

 

 

the area defined by AAR0.

 

 

 

Note: Do not program the value of these bits as zero, since SRAM memory

 

 

 

access requires at least one wait state.

 

 

 

When selecting four through seven wait states, one additional wait state is inserted

 

 

 

at the end of the access. When selecting eight or more wait states, two additional

 

 

 

wait states are inserted at the end of the access. These trailing wait states increase

 

 

 

the data hold time and the memory release time and do not increase the memory

 

 

 

access time.

 

 

 

 

4.6.2DRAM Control Register (DCR)

The DRAM controller is an efficient interface to dynamic RAM devices in both random read/write cycles and Fast Access mode (Page mode). An on-chip DRAM controller controls the page hit circuit, the address multiplexing (row address and column address), the control signal generation (CAS and RAS) and the refresh access generation (CAS before RAS) for a variety of DRAM module sizes and access times. The on-chip DRAM controller configuration is determined by the DRAM Control Register (DCR). The DRAM Control Register (DCR) is a 24-bit read/write register that controls and configures the external DRAM accesses. The DCR bits are shown in Figure 4-7.

Note: To prevent improper device operation, you must guarantee that all the DCR bits except BSTR are not changed during a DRAM access.

23

22

21

20

19

18

17

16

15

14

13

12

 

 

 

 

 

 

 

 

 

 

 

 

BRP

BRF7

BRF6

BRF5

BRF4

BRF3

BRF2

BRF1

BRF0

BSTR

BREN

BME

 

 

 

 

 

 

 

 

 

 

 

 

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

BPLE

 

BPS1

BPS0

 

 

 

 

BRW1

BRW0

BCW1

BCW0

 

 

 

 

 

 

 

 

 

 

 

 

Reserved bit. Read as zero; write to zero for future compatibility

Figure 4-7.DRAM Control Register (DCR)

4-24

DSP56301 User’s Manual

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Motorola DSP56301 user manual Dram Control Register DCR, BRP BRF7 BRF6, BRF3 BRF2 BRF1, Bstr Bren BME Bple BPS1, BCW0
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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