Manuals / Motorola / Home Audio / Stereo System

Motorola DSP56301 user manual Essi Programming Model, Essi Control Register a CRA, WL2 WL1 WL0 ALC

Models: DSP56301

1 372

Download 372 pages 304 b

Page 212

Image 212

ESSI Programming Model

7.5ESSI Programming Model

The ESSI is composed of the following registers:

Two control registers (CRA, CRB), page 14 and page 18

One status register (SSISR), page 28

One Receive Shift Register, page 29

One Receive Data Register (RX), page 30

Three Transmit Shift Registers, page 30

Three Transmit Data Registers (TX0, TX1, TX2), page 30

One special-purpose Time Slot Register (TSR), page 33

Two Transmit Slot Mask Registers (TSMA, TSMB), page 33

Two Receive Slot Mask Registers (RSMA, RSMB), page 35

This section discusses the ESSI registers and describes their bits. Section 7.6, GPIO Signals and Registers, on page 7-36covers ESSI GPIO.

7.5.1ESSI Control Register A (CRA)

The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that direct the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word length, and number of words per frame for serial data.

23	22	21	20	19	18	17	16	15	14	13	12

	SSC1	WL2	WL1	WL0	ALC		DC4	DC3	DC2	DC1	DC0
11	10	9	8	7	6	5	4	3	2	1	0

PSR				PM7	PM6	PM5	PM4	PM3	PM2	PM1	PM0

—Reserved bit; read as 0; write to 0 for future compatibility. (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)

Figure 7-2.ESSI Control Register A(CRA)

7-14	DSP56301 User’s Manual

Page 212

Image 212

Motorola DSP56301 Essi Programming Model, Essi Control Register a CRA, WL2 WL1 WL0 ALC, PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Contents

DSP56301 User’s Manual Revision 3, MarchHow to reach us USA/EUROPEJapan ASIA/PACIFICPage Page Contents Chapter Memory Configuration Chapter Core ConfigurationChapter Programming the Peripherals Chapter Host Interface HI32Chapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Index Chapter Triple Timer ModuleChapter a Bootstrap Program Chapter B Programming Reference Figures DSP56301 User’s ManualXii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables TablesEssi Clock Sources Manual Organization OverviewHigh True/Low True Signal Conventions Signal/Symbol Logic State Signal State VoltageManual Conventions Ground2Ground PIN is a generic term for any pin on the chipDSP56300 Core Features Size Cache Program RAM Instruction Data RAM Switch Size Cache SizeCE = MS = DSP56300 Core Functional Blocks Data ALUMultiplier-Accumulator MAC Address Generation Unit AGUData ALU Registers Program Control Unit PCU PLL and Clock Oscillator Jtag TAP and OnCE ModuleOn-Chip Memory DSP56301 Switch Memory ConfigurationInternal Buses Expansion Area DMAMemory Expansion Area General-Purpose Input/Output Gpio signals PeripheralsHost Interface HI32 Enhance Synchronous Serial Interface EssiTriple Timer Module Serial Communications Interface SCIRelated Documents and Web Sites DSP56301 DocumentationName Description Order Number DSP56300FM/ADDSP56301 Functional Signal Groupings Timers JTAG/OnCE PortEnhanced Synchronous Serial Interfaces ESSI0 ESSI1Port a See -2for a listing of the Host Interface/Port B SignalsDSP56301 Host Interface/Port B Detail Signal Diagram Power Power InputsGround Signals GroundClock Signals Phase-Lock Loop SignalsClock PLLExternal Memory Expansion Port Port a External Address BusExternal Data Bus External Bus ControlSignals are tri-stated Arbitration is reset to the bus slave stateOutput Tri-stated Is an active-low output that is Output Tri-stated Is asserted for half a clockCAS BclkInterrupt and Mode Control Interrupt and Mode ControlSignal State Type During Signal Description Name Nonmaskable Interrupt-AfterHost Interface HI32 10.Host InterfaceCommand 0-3/Byte Enable 0-3 -When the HI32 is programmed HBS HparHdak HperrHserr HirqHstop HWR11.Summary of HI32 Signals and Modes Signal PCI Mode Enhanced Universal Bus Mode Gpio Mode NameHP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9 HAD10 HD2 HIO10HAD11 HD3 HIO11 HAD12 HD4 HIO12Gpio 12.Host Port Pins HI32PCI Bus Command/Byte Enable Host Address Bus Host Target Ready Host Data Bus EnableReserved Host Initiator Ready Host Data Bus DirectionParity Error DMA Request Bus Grant Host Address EnableHost Device Select Host Select Acknowledge Host Lock Bus StrobeHost System Error Host Interrupt Request Bus Request Host Transfer AcknowledgeHreq is deasserted in the same PCI HstrHstop HWR/HRW Host Stop Host Write/Read-WriteHRD/HDS Initialization Device Select Host Read/Data StrobeHost Bus Clock Address/Data Multiplexed Bus Data BusHardware Reset Enhanced Synchronous Serial InterfaceHost Interrupt a Active low, open drain output pin13.Enhanced Synchronous Serial Interface PC0PC1 PC2SCK0 PC3SRD0 PC414.Enhanced Serial Synchronous Interface PD0PD1 PD2SCK1 PD3SRD1 PD415.Serial Communication Interface TimersSerial Communications Interface SCI 16.Triple Timer Signals Timer 0 Schmitt-Trigger Input/Output- When TimerTimer 1 Schmitt-Trigger Input/Output- When Timer Timer 2 Schmitt-Trigger Input/Output- When timer17.JTAG/OnCE Interface Signal Name Type State During Signal Description ResetJtag and OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Memory Configuration Program Memory SpaceInstruction Cache Memory Switch Modes-Program MemoryInternal Program Memory Program Bootstrap ROM Memory Switch Modes-X Data MemoryMemory Configuration Data Memory SpaceInternal Y Data Memory Memory Switch Modes-Y Data MemoryInternal I/O Space-X Data Memory Dynamic Memory Configuration Switching External I/O Space-Y Data MemorySixteen-Bit Compatibility Mode Configuration Internal Memory Configuration SummaryDSP56301 RAM Configurations DSP56301 RAM Address Ranges by ConfigurationRAM DefaultMemory Maps 16-Bit Space With Default RAM 0, 0 None 64K $000-$FFF $000-$7FF16M $000-$800 $000-$BFF16-Bit Space With Switched Program RAM 0, 1 None 64K $000-$7FF $000-$BFFInstruction Cache Enabled 1, 0 $000-$BFF $000-$7FF Not addressable16-Bit Space With Instruction Cache Enabled 1, 0 Addressable $000-$3FF $000-$BFF Not addressable$0400 $0000 Core Configuration Core ConfigurationReset Description Vector Operating ModesDSP56301 Operating Modes ModeOperating Mode Definitions Mode DescriptionDSP Clkout rate must be 5/3 of the PCI clock Address attributes selected defaultLow. The DSP56301 is written with 24-bit-wide words Bootstrap Program Central Processor Unit CPU Registers Status Register SRDMA OMR Cache Enable Sixteen-Bit Arithmetic ModeDo Forever Flag Do Loop FlagSixteen-Bit Compatibility Mode Scaling Mode Scaling Rounding Bit SEquation ModeInterrupt Mask Priority Exceptions Exceptions Masked PermittedBit Number Bit Name Reset Value Description Limit Scaling Mode Integer PortionExtension UnnormalizedOperating Mode Register OMR Operating Mode Register OMR Bit DefinitionsStack Extension Enable Stack Extension Wrap FlagAddress Trace Enable Address Attribute Priority DisableAsynchronous Bus Arbitration Enable Stack Extension Overflow FlagCache Burst Mode Enable Memory Switch ModeBus Release Timing Synchronize SelectConfiguring Interrupts Bit Number Bit Name Reset Value Description Stop Delay ModeExternal Bus Disable Chip Operating ModeInterrupt Priority Registers Iprc and Iprp Interrupt Sources Interrupt Table Memory MapInterrupt Priority Level Bits VBA$1A VBA$1CVBA$1E VBA$2APriority Interrupt Source Processing Interrupt Source Priorities Within an IPLInterrupt Source Priorities Within an IPL Host command interrupt TIMER0 overflow interruptTIMER0 compare interrupt TIMER1 overflow interruptPLL Control Register Pctl PLL Control Register Pctl Bit DefinitionsBus Interface Unit BIU Registers Bus Control RegisterBus Default Area Wait State Control Bus Area 3 Wait State ControlBus Area 2 Wait State Control Bus Area 1 Wait State ControlDram Control Register DCR BRP BRF7 BRF6BRF3 BRF2 BRF1 Bstr Bren BME Bple BPS110.DRAM Control Register DCR Bit Definitions Bus Page Logic Enable Bus Dram Page SizeBus Row Out-of-page Wait States Bus Column In-Page Wait StateBus Number of Address Bits to Compare Address Attribute Registers AAR0-3Bus Address to Compare Bus Packing Enable Bus Y Data Memory EnableBus X Data Memory Enable Bus Program Memory EnableDMA Control Registers 5-0 DCR5-0 DIE DTM2 DTM1 DTM0Dcon DAM5 DAM4 DAM3 DAM2 DAM1 DAM0DMA Interrupt Enable DMA Transfer ModeDTM2-0 Trigger Cleared Transfer Mode After 12.DMA Control Register DCR Bit DefinitionsNumber Value DMA Channel PriorityDMA address generation logic, buses, and so forth DPR1-0 Channel PriorityDcon DMA Continuous Mode EnableOMR CDP1-0 CP1-0 Core Priority DRS4-0 Requesting Device Three-Dimensional ModeDMA Request Source DSS1 DSS0 Device Identification Register IDRDDS1 DDS0 Jtag Identification ID Register Jtag Boundary Scan Register BSRVersion Information Design Center Number Identity See NoteJtag Boundary Scan Register BSR DSP56301 User’s Manual Peripheral Initialization Steps Programming the PeripheralsMapping the Control Registers Data Transfer MethodsPolling Data MemoryInterrupts Advantages and Disadvantages General-Purpose Input/Output Gpio3 DMA Port B Signals and Registers Port E Signals and Registers Port C Signals and RegistersPort D Signals and Registers Triple Timer Signals and Registers Timer GpioGeneral-Purpose Input/Output Gpio DSP56301 User’s Manual Features Host Interface HI32HI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview PCI Configuration Space DSP-Side RegistersDSP DMA Data Bus DSP Global Data Bus Data transfer format converterData Transfer Paths Host-to-DSP Data PathDSP-To-Host Data Path HI32 PCI Master Data Transfer Formats DpmcFC1 FC0 Two least significant bytes of two HrxmHTF1 HTF0 Transmit Data Transfer FormatHctr Receive Transfer Data Formats DSP to Host Data Transfer FormatHRF Three least significant Hrxs bytesReceive Transfer Data Formats Reset States Type Entered when DescriptionDSP-Side Operating Modes HRST/HRSTTerminate and Reset Dctrhm = $0 PCI Mode Dctrhm = $1HI32 Mode PCIExample 6-1. PCI /DMA Throughput 32-Bit Multfactor Gpio Mode Dctrhm = $4 Self-Configuration Mode Dctrhm = $5Example 6-3. Self-Configuration Procedure for PCI Mode Host Port Pin Functionality Host Port PinsPCI Bus Universal Bus Mode DSP56301 ISA Master SlaveHI32 Programming Model, DSP Side Memory Register Address ModeHI32 DSP-Side Programming Model Bit Number Bit Name Mode Description ValueDSP Control Register Dctr 10.DSP Control Register Dctr Bit Definitions Host Data Strobe Mode HtapHost Transfer Acknowledge Polarity Host Read/Write PolaritySlave Receive Interrupt Enable Slave Transmit Interrupt EnableHost Command Interrupt Enable DSP PCI Control Register DpcrInsert Address Enable Receive Buffer Lock Enable11.DSP PCI Control Register Dpcr Bit Definitions IAEMaster Wait State Disable Master Access Counter EnableForce HserrTransfer Complete Interrupt Enable Transaction Termination Interrupt EnableTransaction Abort Interrupt Enable Parity Error Interrupt EnableBL1 BL0 DSP PCI Master Control Register DpmcBL4 12.DSP PCI Master Control Register Dmpc Bit Definitions Data Transfer Format ControlA PCI DSP-to-Host transaction A PCI Host-to-DSP transactionPCI Data Burst Length DSP PCI Transaction Address HighDSP PCI Address Register Dpar 13.DSP PCI Address Register Dpar Bit DefinitionsBE2 BE1 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0PCI Bus Command C3-0 Command TypeDSP PCI Transaction Address Low AR1 AR0Bit Bit Name Reset Mode Description Number Value DSP Status Register DSR14.DSP Status Register DSR Bit Definitions 2322212019181716Srrq UBM Slave Receive Data RequestMode Description Number Value Host Command Pending14. DSP Status Register DSR Bit Definitions Slave Transmit Data RequestDSP PCI Status Register Dpsr 15.DSP PCI Status Register Dpsr Bit DefinitionsRdcq MDT Hdtc Trty Tdis TAB MAB Aper Marq Mrrq Mtrq MWSMaster Data Transferred PCI Host Data Transfer CompletePCI Time Out Termination PCI Target RetryPCI Data Parity Error PCI Address Parity ErrorPCI Target Disconnect PCI Target AbortDSP Receive Data Fifo Drxr 15. DSP PCI Status Register Dpsr Bit DefinitionsPCI Master Wait States PCI Master Receive Data RequestDSP Master Transmit Data Register Dtxm DSP Slave Transmit Data Register Dtxs16.DATH and Dirh Functionality DSP Host Port Gpio Direction Register DirhDSP Host Port Gpio Data Register Dath Memory Register Host-Side Programming Model17.HI32 Programming Model, Host-Side Registers Host-Side Programming Model 18.PCI Bus Commands Executed as Command TypeHC3/HBE3-HC0/HBE0 Ignored19. Host-Side Registers PCI Memory Address Space 20. Host-Side Registers PCI Configuration Address Space21. Host-Side Registers Universal Bus Mode Address Space 1 HI32 Control Register Hctr 13.Host Interface Control Register HctrBit Bit Name Reset Mode Description Number Target Wait State Disable22.Host Interface Control Register Hctr Bit Definitions Twsd PCIHost Receive Data Transfer Format Host Transmit Data Transfer Format Slave Fetch Type Inserted AddressSFT UBM Universal Bus mode Fetch SFT = Cleared when the DSP56300 core writes toReset, and Strq and Hstrhrrq are cleared Data path is lost when the reset state isHirq Dmae UBMDmae Haen Receive Req uest Enable Rreq UBMDmae Treq Rreq Hirq Pin Hdrq pinHost Interface Status Register Hstr Hreq Hint HF5 HF4 HF3Trdy UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCI23.Host Interface Status Register Hstr Bit Definitions Host RequestHost interrupt a Treq Rreq HreqTransmitter Ready Host Receive Data RequestHost Transmit Data Request Host Command Vector Register Hcvr 15.Host Command Vector Register Hcvr24.Host Command Vector Register Hcvr Bit Definitions Host Command VectorBit Bit Name Reset Value Mode Description Number Hnmi UBMHost Command When the DSP56300 core acknowledges the host commandHost Master Receive Data Register Hrxm Host Slave Receive Data Register HrxsHost Transmit Data Register Htxr PCI Mode Dctrhm = $1 Universal Bus mode Dctrhm = $2 or $3Device ID/Vendor ID Configuration Register CDID/CVID Status/Command Configuration Register CSTR/CCMRDPE SSE RMA RTA STA DPR FbbcDetected Parity Error Signaled System ErrorSignalled Target Abort Received Master AbortSystem Error Enable Wait Cycle Control hardwired to zeroParity Error Response Bus Master EnableClass Code/Revision ID Configuration Register CCCR/CRID Header Type hardwired to $00 HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0HT7-0 Read-only bits that identify the layout of bytes $10-$3FCcls Latency Timer HighCache Line Size Memory Space Base Address Configuration Register Cbma Universal Bus Mode Base AddressPM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Base Address High/Low29. Memory Space Base Address Configuration Register Cbma Memory Base Address Low Hardwired to zerosPre-Fetch Hardwired to zero Memory Space Hardwired to zerosExample 6-5. Code for Setting the Csid Interrupt Line-Interrupt Pin Configuration RegisterCILP IL5 IL4IL1 IL0 MaxlatHI32 Programming Model/Quick Reference HS PH PSDctr Hcie UBM HrspRble Dpcr MtieClrt Dpmc DparDSR HCP HactDpsr Aper DperHdtc RdcqTreq DmaeISA/EISA SFTHcvr HnmiHrxm HrxsCcmr RMA CccrChty Cbma MSIGDB DDB Rclk Rsma Rsmb Tsma Tclk STDTsmb TX0 CRA SC0Essi Enhancements Essi Data and Control Signals Serial Transmit Data Signal STDSerial Receive Data Signal SRD Serial Clock SCKSerial Control Signal SC0 Serial Control Signal SC1SYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Mode and Signal DefinitionsControl Bits Essi Signals Serial Control Signal SC2 Essi After ResetOperation InitializationExceptions Operation Write data to all enabled transmit registers Normal/Network/On-Demand Mode Selection Operating Modes Normal, Network, and On-DemandFrame Sync Selection Frame Sync Signal FormatSynchronous/Asynchronous Operating Modes Frame Sync Polarity Frame Sync Length for Multiple DevicesWord Length Frame Sync and Data Word Timing Byte Format LSB/MSB for the Transmitter FlagsEssi Programming Model Essi Control Register a CRAWL2 WL1 WL0 ALC PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0Essi Control Register a CRA Bit Definitions Select SC1Word Length Control Essi Word Length SelectionAlignment Control Frame Rate Divider ControlPrescaler Range Prescale Modulus SelectCRBTE1 CRBOF0 SSISRIF0 Crbsyn =Rclock TclockEssi Control Register B CRB ShfdOF1 OF0 ESSI0 X$FFFFB6, ESSI1 X$FFFFA6Essi Control Register B CRB Bit Definitions Transmit Interrupt Enable Receive EnableTransmit 0 Enable TIETransmit 1 Enable Transmit 2 EnableMode Select Synchronous/AsynchronousFSL1 FSL0 Serial Control Direction OF1Serial Output Flag OF0TX Frame Sync TX Serial Data Serial Clock RX, TX Frame Sync RX, TX Serial DataSerial Clock RX Frame Sync RX Serial Data CRB SYN Bit Operation Essi BitReceiver Interrupt or DMA Request and Flags Set Bit OperationSSI Control Register B CRB READ/WRITE Frame Sync FSL0 = 0, FSL1 = Data Out Flags Frame Sync FSL0 = 0, FSL1 = Data FlagsReceiver Overrun Error Flag Transmitter Underrun Error FlagEssi Status Register Ssisr Receive Data Register FullEssi Receive Shift Register Receive Frame Sync FlagTransmit Frame Sync Flag Serial Input FlagEssi Receive Data Register RX Essi Transmit Shift RegistersReceive Registers Transmit RegistersTransmit Middle Byte Transmit Low Byte Register 24 Bit WL0Least Significant MSBEssi Transmit Data Registers TX2-0 Essi Time Slot Register TSRTransmit Slot Mask Registers TSMA, Tsmb TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS015.ESSI Transmit Slot Mask Register B Tsmb Receive Slot Mask Registers RSMA, Rsmb RS7 RS6RS1 RS0 RS15 RS14 RS13 RS12 RS11 RS10Gpio Signals and Registers Port Control Registers Pcrc and PcrdESSI0/ESSI1 Essi Port Signal ConfigurationsPort Direction Registers Prrc and Prrd Port Data Registers Pdrc and Pdrd 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFADSerial Communication Interface SCI Serial Communication Interface SCIMultidrop Mode Synchronous ModeAsynchronous Mode I/O Signals Wired-OR ModeAddress Mode Wakeup Transmitting Data and Address CharactersSCI Serial Clock Sclk Receive Data RXDTransmit Data TXD SCI After Reset SCI Registers After ResetReie Sckp Stir Tmie TIE RIE Ilie Woms RWU Wake SBK SsftdSCI Initialization Preamble, Break, and Data Transmission Priority Bootstrap Loading Through the SCI Boot Mode 2 or a ExceptionsSCI Programming Model Bit Synchronous Data Shift Register Mode WDS2 WDS1 WDS0Bit Asynchronous 1 Start, 8 Data, 1 Stop Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 StopSCI Data Word Formats Ssftd = 0 Stir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 SCI Control Register SCRReie Timer Interrupt Enable SCI Transmit Interrupt EnableSCI Receive Interrupt Enable Idle Line Interrupt EnableWoms Receiver EnableWired-OR Mode Select Receiver Wakeup Enable Wakeup Mode SelectSend Break SCI Shift DirectionWDS1 WDS0 Mode Word FormatsWord Select Idle Rdrf Tdre Trne SCI Status Register SSRSCI Status Register SCI Status Register SSR Bit Definitions Transmitter Empty Idle Line FlagTdre SCI Clock Control Register Sccr TCM RCM SCP CODTCM RCM SclkBit Counter Divide byCD11-0 Sckp = 0 + Sckp =RX, TX Data Ssftd = X1 Clock X16 Clock Sckp =SCI Receive Data Shift Register SCI Data RegistersSCI Receive Register SRX SCI Transmit Register STX Sclk TXD RXD Port E Control Register PcrePE2 PE1 PE0 Port E Direction Register Prre Port E Data Register PdrePRRE1 PRRE0 PDRE1 PDRE0Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer ModuleTriple Timer Module Block Diagram Individual Timer Block DiagramGDB TpcrTimer After Reset Timer Module Block DiagramTimer Initialization Timer ExceptionsTCSR0 Tcie Triple Timer Modes Timer Gpio ModeTC3 TC2 TC1 TC0 TIOTCR Tcpr Mode 0 internal clock, no timer output TRM =TLR Output Timer Pulse ModeMode 1 internal clock TRM = Pulse width = timer clock Period Timer Toggle Mode Mode 2 internal clock TRM = 1 first eventToggle Timer = write preload = write compare Clock CLK/2 or prescale CLK= write compare Clock CLK/2 or prescale CLK Mode 2 internal clock TRM == write preload Timer Event Counter Mode Mode 3 internal clock TRM =Input External TIO Cpuclk +10.Event Counter Mode, TRM = = write compare ClockSignal Measurement Modes Measurement Input Width ModeInput Input width MeasurementMode 4 internal clock TRM = Mode 4 internal clock TRM = 1 first eventMeasurement Input Period Mode Mode 5 internal clock TRM =First event = write preload = write compare Input period Measurement InternalReads TCR period Counting, doesMay occur TOF=1 Measurement Capture Mode Mode 6 internal clock TRM =Interrupt Service reads TCR delay = M N clock periods InternalPulse width modulation Pulse Width Modulation PWM, ModePWM Mode 7 internal clock TRM = 16.Pulse Width Modulation Toggle Mode, TRM =17.Pulse Width Modulation Toggle Mode, TRM = Watchdog Pulse Mode Watchdog ModesPulse Watchdog Output Internal= write preload First event Mode 9 internal clock TRM =Software does not reset watchdog timer watchdog times out Watchdog Toggle Mode Mode 10 internal clock TRM =Watchdog Output ToggleTriple Timer Module Programming Model Special CasesDMA Trigger Prescaler CounterTimer Prescaler Load Register Tplr23 22 21 20 19 18 17 Tplr = $FFFF83Timer Prescaler Load Register Tplr Prescaler SourcePS1 PS0 Prescaler Preload ValueTimer Prescaler Count Register Tpcr Timer Control/Status Register TcsrTCF TOF PCE TRM INVTimer Compare Flag Timer Overflow FlagPrescaler Clock Enable Data OutputInverter Timer Reload ModeDirection Timer Control Number FunctionTimer Compare Interrupt Enable Timer Overflow Interrupt EnableTimer Enable TIO Programmed as Input TIO Programmed as Output Mode INV =Positive polarity Timer Load Register TLRPulse generated by Timer has Timer has negative Timer Compare Register Tcpr Timer Count Register TCRAppendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Chapter B Programming ReferenceTable B-1.Guide to Programming Sheets Bit Address Register Name Internal I/O Memory MapTable B-2. Internal I/O Memory Map X Data Memory Table B-2.Internal I/O Memory Map X Data Memory Peripheral Bit Address Register Name$FFCD $FFFFCD $FFCC $FFFFCC$FFCB $FFFFCB $FFCA $FFFFCAEssi $FFBC $FFFFBC $FFBB $FFFFBB$FFBA $FFFFBA $FFB9 $FFFFB9Essi $FFAC $FFFFAC $FFAB $FFFFAB$FFAA $FFFFAA $FFA9 $FFFFA9$FFFF92 $FFFF91$FFFF90 $FF8F $FFFF8FInterrupt Sources and Priorities Table B-3. Interrupt SourcesTable B-3.Interrupt Sources VBA$6AVBA$6C VBA$6ENonmaskable Host Command Interrupt Table B-4.Interrupt Source Priorities Within an IPLESSI0 receive last slot interrupt Programming Sheets Figure B-1.Status Register SRExternal Bus Disable Stop DelayMemory Switch Mode Burst Mode EnableIrqd Mode Irqc ModeIrqb Mode Irqa ModeInterrupt Priority Register Iprp $FFFFFE Read/Write Triple Timer IPLHost IPL PLL Control Register Pctl $FFFFFD Read/Write Crystal Range Bit XtlrDefault Area Wait Control, Bits Bus Control Register BCR $FFFFFB Read/WriteBus Request Hold, Bit Bus Lock Hold, BitDram Control Register DCR $FFFFFA Read/Write Bus Packing Enable, Bit Bus Y Data Memory Enable, BitBus X Data Memory Enable, Bit Bus Program Memory Enable, BitReset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/Write DMA Control Registers DCR5-DCR0DSP Control Register Dctr Read/Write Address X FFFFC5 Application= Enables master receive interrupts DSP PCI Control Register Dpcr Address XFFFFC6 Read/WriteFigure B-12.DSP PCI Master Control Register Dpmc PCI Bus Command, Bits Figure B-13.DSP PCI Address Register DparHI32 Control Register Hctr Read/Write HI32 Command Vector Register Hcvr Read/Write Host Non-Maskable Interrupt, BitDetected Parity Error, Bit Signaled System Error, BitSignalled Target Abort, Bit System Error Enable, BitLatency Timer High, Bits Read/WriteHeader Type, Bits Cache Line Size, BitsHI32 Memory Space Base Address Configuration Register Cbma Reset = $00000000PCI Mode Base Address High, Bits Pre-fetch, Bit Memory Space Indicator, BitSubsystem ID Register, Bits 31-16 Specifies the subsystem ID Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/Write ESSI1-X$FFFFA5 Read/WriteESSI1-X$FFFFA6 Read/Write Essi Control Register B CRBxESSI0-X$FFFFB6 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/Write ESSI1-X$FFFFA4 Read/WriteEssi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write ESSI1-X$FFFFA3 Read/WriteSCI Control Register SCR $FFFF9C Read/Write Clock Out Divider SCI Clock Control Register Sccr Address X$FFFF9B Read/WriteReceiver Clock Mode/Source Figure B-25.Timer Prescaler Load Register Tplr Timer Prescaler Load Register Tplr $FFFF83 Read/WriteTimer Control/Status Register TCSR0$FFFF8F Read/Write TCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/WriteTimer Load Register TLR0-2 TLR0-X$FFFF8E Write Only TLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write OnlyHost Data Register HDR $FFFFC9 Write Port B HI08Host Data Direction Register Hddr X$FFFFC8 Write Port C ESSI0 Port C Control Register Pcrc $FFFFBF Read/WritePort C Direction Register Prrc $FFFFBE Read/Write Port C Gpio Data Register Pdrc $FFFFBD Read/WritePort D ESSI1 Port D Control Register Pcrd $FFFFAF Read/WritePort D Direction Register Prrd $FFFFAE Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/WritePort E SCI Port E Control Register Pcre $FFFF9F Read/WritePort E Direction Register Prre $FFFF9E Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/WriteProgramming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual