Motorola DSP56301 user manual Dpmc, Dpar, Dsr Hcp, Hact, Dpsr MWS

HI32 Programming Model/Quick Reference

HI32 Registers—Quick Reference

Reg				Bit				Comments	Reset Type
	Num	Mnemonic		Name	Val	Function			HS	PH	PS
DPMC	15-0	AR[31–16]		DSP PCI Transaction				written only if	$0000	-	-
				Address (High)				MARQ = 1
	21-16		BL[5–0]	PCI Data Burst Length				written only if	$0	-	-
								MARQ = 1
			FC[1–0]	Data Transfer Format		Transmit	Receive	written only if
				Control	00	32 bit mode	32 bit mode	MARQ = 1
	23-22				01	3 Right, zero ext	.3 LSBs		$0	-	-
					10	3 Right, sign ext	.3 LSBs
					11	3 Left, zero filled	3 MSBs
DPAR	15-0	AR[15–0]		DSP PCI Transaction				written only if	$0000	-	-
				Address (Low)				MARQ = 1
	19-16		C[3–0]	PCI Bus Command				written only if	$0	-	-
								MARQ = 1
				PCI Byte Enables				written only if	$0	-	-
	23-20		BE[3–0]
								MARQ = 1
DSR			HCP	Host Command	0	no host command pending		cleared when	-	-	0
	0			Pending	1	host command pending		the HC interrupt
								request is
								serviced
			STRQ	Slave Transmit Data	1	slave transmit FIFO is not full		cleared if the	11	-	1(1)
	1			Request	0	slave transmit FIFO is full		DTXS is filled by
								core writes
			SRRQ	Slave Receive Data	0	slave receive FIFO is empty		cleared if the	0	-	0
				Request	1	slave receive FIFO is not		DRXR is
						empty		emptied by core
	2							reads or the
								data to be read
								from the DRXR
								is master data
	5-3		HF[2–0]	Host Flags					-	$0	-
	23		HACT	HI32 Active	0	HI32 is in personal reset (PS)			0	-	0
					1	HI32 is active
DPSR			MWS	PCI Master Wait	0	HI32 is asserting			0	-	0
	0						HIRDY
				States	1
						HI32 is deasserting HIRDY
			MTRQ	PCI Master Transmit	1	master transmit FIFO is not		cleared if the	1(1)	-	1(1)
	1			Data Request		full		DTXM is filled by
					0	master transmit FIFO is full		core writes
			MRRQ	PCI Master	0	master receive FIFO is empty		cleared if the	0	-	0
				Receive Data Request	1	master receive FIFO is not		DRXR is
						empty		emptied by core
	2							reads or the
								data to be read
								from the DRXR
								is slave data.
			MARQ	PCI Master Address	1	Core can initiate new			0	0	0
	4			Request		transaction
					0	Core cannot initiate new
						transaction

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