Host-Side Programming Model

6.8.10Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)

r (

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HT7

HT6

HT5

HT4

HT3

HT2

HT1

HT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LT7

LT6

LT5

LT4

LT3

LT2

LT1

LT0

CLS7 CLS6 CLS5 CLS4 CLS3 CLS2 CLS2 CLS0

Not implemented. Read and write as zero for future compatibility.

Figure 6-19.Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)

A PCI-standard read/write register mapped into the PCI configuration space in PCI mode or in mode 0 (DCTR[HM] = $1 or $0). The CHTY/CLAT/CCLS is accessed when a configuration read/write command is in progress and the PCI address is $0C. In Self-Configuration mode (DCTR[HM]] = $5), the DSP56300 core can indirectly access the CLAT (see Section 6.5.5, Self-Configuration Mode (DCTR[HM] = $5), on page 6-16). The CHTY/CLAT/CCLS is written in accordance with the byte enables. Byte lanes that are not enabled are not written and the corresponding bits remain unchanged. The host can access CHTY/CLAT/CCLS only when the HI32 is in PCI mode (HM≠$1).

Table 6-28.Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)

Bit Definitions

Bit Number

Bit Name

Reset Value

Description

 

 

 

 

 

 

 

 

31–24

 

0

Not implemented. Write to zero for future compatibility.

 

 

 

 

23–16

HT[7–0]

0

Header Type (hardwired to $00)

 

 

 

Read-only bits that identify the layout of bytes $10-$3F in the

 

 

 

configuration space and also whether the device contains multiple

 

 

 

functions.

 

 

 

 

6-68

DSP56301 User’s Manual

Page 185 Page 187
Page 186
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Motorola DSP56301 user manual HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0, HT7-0, Header Type hardwired to $00, Functions
Page 185 Page 187

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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