Motorola DSP56301 user manual Chapter Memory Configuration, Chapter Core Configuration

2.8	Enhanced Synchronous Serial Interface 0	2-22
2.9	Enhanced Synchronous Serial Interface 1	2-25
2.10	Serial Communications Interface (SCI)	2-27
2.11	Timers	2-27
2.12	JTAG and OnCE Interface	2-29

Chapter 3

Memory Configuration

3.1	Program Memory Space	3-1
3.1.1	Internal Program Memory	3-2
3.1.2	Memory Switch Modes—Program Memory	3-2
3.1.3	Instruction Cache	3-2
3.1.4	Program Bootstrap ROM	3-3
3.2	X Data Memory Space	3-3
3.2.1	Internal X Data Memory	3-3
3.2.2	Memory Switch Modes—X Data Memory	3-3
3.2.3	Internal I/O Space—X Data Memory	3-4
3.3	Y Data Memory Space	3-4
3.3.1	Internal Y Data Memory	3-4
3.3.2	Memory Switch Modes—Y Data Memory	3-4
3.3.3	External I/O Space—Y Data Memory	3-5
3.4	Dynamic Memory Configuration Switching	3-5
3.5	Sixteen-Bit Compatibility Mode Configuration	3-6
3.6	Internal Memory Configuration Summary	3-6
3.7	Memory Maps	3-7

Chapter 4

Core Configuration

4.1	Operating Modes	4-2
4.2	Bootstrap Program	4-5
4.3	Central Processor Unit (CPU) Registers	4-6
4.3.1	Status Register (SR)	4-6
4.3.2	Operating Mode Register (OMR)	4-12
4.4	Configuring Interrupts	4-15
4.4.1	Interrupt Priority Registers (IPRC and IPRP)	4-16
4.4.2	Interrupt Table Memory Map	4-17
4.4.3	Processing Interrupt Source Priorities Within an IPL	4-19
4.5	PLL Control Register (PCTL)	4-21
4.6	Bus Interface Unit (BIU) Registers	4-22
4.6.1	Bus Control Register	4-22
4.6.2	DRAM Control Register (DCR)	4-24
4.6.3	Address Attribute Registers (AAR[0–3])	4-27
4.7	DMA Control Registers 5–0(DCR[5–0])	4-29
4.8	Device Identification Register (IDR)	4-34

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