Manuals / Motorola / Home Audio / Stereo System

Motorola DSP56301 user manual Memory Space Base Address Configuration Register Cbma

Models: DSP56301

1 372
Download 372 pages 304 b
Page 188
Image 188

Host-Side Programming Model

6.8.11Memory Space Base Address Configuration Register (CBMA)

r

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

PM31 PM30 PM29 PM28 PM27 PM26 PM25 PM24 PM23/ PM22/ PM21/ PM20/ PM19/ PM18/ PM17/ PM16/ GB10 GB9 GB98 GB7 GB6 GB5 GB4 GB3

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PM15 PM14 PM13 PM12 PM11 PM10 PM9

PM8

PM7

PM6

PM5

PM4

PF

MS1

MS0

MSI

Hardwired to zero

Figure 6-20.Memory Space Base Address Configuration Register (CBMA)

A PCI-standard read/write register mapped into the PCI configuration space in PCI mode or in mode 0 (HM = $1 or $0). The CBMA is accessed if a configuration read/write command is in progress and the PCI address is $10. The CBMA controls the HI32 mapping into the PCI memory space and the Universal Bus mode space. In Self-Configuration mode (DCTR[HM] = $5), the DSP56300 core can indirectly access the CBMA (see Section 6.5.5, Self-Configuration Mode (DCTR[HM] = $5), on page 6-16). The CBMA is written in accordance with the byte enables. Byte lanes that are not enabled are not written and the corresponding bits remain unchanged. The host can access CBMA only when the HI32 is in PCI mode (HM≠$1).

Table 6-29.Memory Space Base Address Configuration Register (CBMA)

Bit Definitions

Bit Number

Bit Name

Reset Value

Description

 

 

 

 

 

 

 

 

31–16

PM[31–16]

0

Memory Base Address High/Low

 

 

 

Defines the HI32 base address when it is mapped into the PCI memory

 

 

 

space. PM[15–4] are hardwired to zero, and the PCI master can write to

 

 

 

PM[31–16] during system configuration. The HI32 target occupies

 

 

 

16384 32-bit words of the PCI memory space. The HI32 is selected by

 

 

 

the 20 most significant PCI address pins HAD[31–12]. The twelve least

 

 

 

significant address pins HAD[11–0] select the HI32 registers on the

 

 

 

host side (see Figure 6-2on page 6-19). The personal hardware reset

 

 

 

clears PM[31–16].

23–16

GB[10–3]

 

Universal Bus Mode Base Address

 

 

 

Defines the HI32 base address when it is mapped into the Universal

 

 

 

Bus mode space. The remaining CBMA bits are ignored in the

 

 

 

Universal Bus modes. The HI32 slave occupies eight locations in the

 

 

 

Universal Bus mode space. The HI32 is selected by the eight most

 

 

 

significant address pins HA[10–3]. The three least significant address

 

 

 

pins HA[2–0] select the HI32 registers on the host side. The personal

 

 

 

hardware reset clears GB[10–3].

 

 

 

 

6-70

DSP56301 User’s Manual

Page 187 Page 189
Page 188
Image 188
Motorola DSP56301 user manual Memory Space Base Address Configuration Register Cbma, PM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI
Page 187 Page 189

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.