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Motorola DSP56301 user manual Dmae UBM, Dmae Haen, Hirq

Models: DSP56301

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Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit

Bit Name

Reset

Mode

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

6

DMAE

0

UBM

DMA Enable (ISA/EISA)

Used by the host processor to enable the HI32 ISA/EISA DMA-type accesses in a Universal Bus mode (DCTR[HM] = $2 or $3). If the host drives the HAEN pin low, the HI32 responds when it identifies its address (such as ISA/EISA I/O-type accesses). The HI32 does not respond to ISA/EISA DMA-type accesses. When the HAEN pin is high:

νIf DMAE is cleared, the HI32 cannot be accessed.

νIf DMAE is set, the HI32 responds to ISA/EISA DMA-type accesses.

 

 

 

 

When DMAE is cleared, the HDRQ pin is deasserted, HIRQ is active.

 

 

 

 

If DMAE is set, the HIRQ pin is deasserted, HDRQ is active. This allows

 

 

 

 

the HI32 to generate host DMA requests during ISA/EISA I/O-type

 

 

 

 

accesses. A typical application is an external host write to the HI32 using

 

 

 

 

a polling procedure and external DMA reads from the HI32. An external

 

 

 

 

bus controller arbitrates between the two and sets or clears HAEN

 

 

 

 

accordingly. If both DMAE and HAEN are set, HTA is released (high

 

 

 

 

impedance) because DMA devices cannot extend DMA cycles

 

 

 

 

(ISA/EISA). The personal hardware reset clears DMAE.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMAE

HAEN

ISA/EISA Access Type

 

 

 

 

 

and HDRQ

 

 

 

 

 

HIRQ

 

 

 

 

bit

 

pin

 

 

 

Functionality

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

The HI32 responds when it

 

 

 

 

is active,

 

 

 

 

 

HIRQ

 

 

 

 

 

 

 

identifies its address

 

HDRQ is deasserted

 

 

 

 

 

 

 

(that is, ISA/EISA I/O-type

 

 

 

 

 

 

 

 

 

 

 

 

 

access)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

The HI32 does not respond to

 

 

 

is active,

 

 

 

 

 

HIRQ

 

 

 

 

 

 

 

any access

 

HDRQ is deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

The HI32 responds when it

 

HDRQ is active,

 

 

 

 

 

 

 

identifies its address

 

HIRQ is deasserted1

 

 

 

 

 

 

 

(that is, ISA/EISA I/O-type

 

 

 

 

 

 

 

 

 

 

 

 

 

access)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

The HI32 responds when

 

HDRQ is active,

 

 

 

 

 

 

 

HDAK is asserted

 

HIRQ is deasserted

 

 

 

 

 

 

 

(that is, ISA/EISA DMA-type

 

 

 

 

 

 

 

 

 

 

 

 

 

access)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 –3

HF[2–0]

0

UBM

Host Flags

 

 

 

 

 

 

 

 

 

 

PCI

General-purpose flags for host-to-DSP communication. The host

 

 

 

 

processor sets and clears HF[2–0]. The personal hardware reset clears

 

 

 

 

HF[2–0].

 

 

 

 

 

 

 

 

6-54

DSP56301 User’s Manual

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Motorola DSP56301 user manual Dmae UBM, Dmae Haen, Hirq
Page 171 Page 173

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.